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annotate test/CodeGen/AMDGPU/llvm.AMDGPU.mul.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents test/CodeGen/R600/llvm.AMDGPU.mul.ll@95c75e76d11b
children
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95c75e76d11b LLVM 3.4
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1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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95c75e76d11b LLVM 3.4
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3 ;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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95c75e76d11b LLVM 3.4
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5 define void @test(<4 x float> inreg %reg0) #0 {
95c75e76d11b LLVM 3.4
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6 %r0 = extractelement <4 x float> %reg0, i32 0
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7 %r1 = extractelement <4 x float> %reg0, i32 1
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8 %r2 = call float @llvm.AMDGPU.mul( float %r0, float %r1)
95c75e76d11b LLVM 3.4
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9 %vec = insertelement <4 x float> undef, float %r2, i32 0
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10 call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
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11 ret void
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12 }
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14 declare float @llvm.AMDGPU.mul(float ,float ) readnone
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15 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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17 attributes #0 = { "ShaderType"="0" }