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annotate test/Transforms/SROA/big-endian.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 95c75e76d11b
children 3a76565eade5
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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1 ; RUN: opt < %s -sroa -S | FileCheck %s
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parents:
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2
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3 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
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4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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5 define i8 @test1() {
95c75e76d11b LLVM 3.4
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parents:
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6 ; We fully promote these to the i24 load or store size, resulting in just masks
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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7 ; and other operations that instcombine will fold, but no alloca. Note this is
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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8 ; the same as test12 in basictest.ll, but here we assert big-endian byte
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parents:
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9 ; ordering.
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10 ;
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parents:
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11 ; CHECK-LABEL: @test1(
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12
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13 entry:
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parents:
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14 %a = alloca [3 x i8]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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15 %b = alloca [3 x i8]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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16 ; CHECK-NOT: alloca
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17
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afa8332a0e37 LLVM 3.8
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18 %a0ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 0
0
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19 store i8 0, i8* %a0ptr
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20 %a1ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 1
0
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parents:
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21 store i8 0, i8* %a1ptr
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22 %a2ptr = getelementptr [3 x i8], [3 x i8]* %a, i64 0, i32 2
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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23 store i8 0, i8* %a2ptr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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24 %aiptr = bitcast [3 x i8]* %a to i24*
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parents: 0
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25 %ai = load i24, i24* %aiptr
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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26 ; CHECK-NOT: store
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parents:
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27 ; CHECK-NOT: load
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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28 ; CHECK: %[[ext2:.*]] = zext i8 0 to i24
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parents:
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29 ; CHECK-NEXT: %[[mask2:.*]] = and i24 undef, -256
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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30 ; CHECK-NEXT: %[[insert2:.*]] = or i24 %[[mask2]], %[[ext2]]
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parents:
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31 ; CHECK-NEXT: %[[ext1:.*]] = zext i8 0 to i24
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parents:
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32 ; CHECK-NEXT: %[[shift1:.*]] = shl i24 %[[ext1]], 8
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parents:
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33 ; CHECK-NEXT: %[[mask1:.*]] = and i24 %[[insert2]], -65281
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parents:
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34 ; CHECK-NEXT: %[[insert1:.*]] = or i24 %[[mask1]], %[[shift1]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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35 ; CHECK-NEXT: %[[ext0:.*]] = zext i8 0 to i24
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parents:
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36 ; CHECK-NEXT: %[[shift0:.*]] = shl i24 %[[ext0]], 16
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parents:
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37 ; CHECK-NEXT: %[[mask0:.*]] = and i24 %[[insert1]], 65535
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parents:
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38 ; CHECK-NEXT: %[[insert0:.*]] = or i24 %[[mask0]], %[[shift0]]
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parents:
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39
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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40 %biptr = bitcast [3 x i8]* %b to i24*
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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41 store i24 %ai, i24* %biptr
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parents: 0
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42 %b0ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 0
afa8332a0e37 LLVM 3.8
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parents: 0
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43 %b0 = load i8, i8* %b0ptr
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parents: 0
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44 %b1ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 1
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parents: 0
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45 %b1 = load i8, i8* %b1ptr
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parents: 0
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46 %b2ptr = getelementptr [3 x i8], [3 x i8]* %b, i64 0, i32 2
afa8332a0e37 LLVM 3.8
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parents: 0
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47 %b2 = load i8, i8* %b2ptr
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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48 ; CHECK-NOT: store
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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49 ; CHECK-NOT: load
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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50 ; CHECK: %[[shift0:.*]] = lshr i24 %[[insert0]], 16
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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51 ; CHECK-NEXT: %[[trunc0:.*]] = trunc i24 %[[shift0]] to i8
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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52 ; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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53 ; CHECK-NEXT: %[[trunc1:.*]] = trunc i24 %[[shift1]] to i8
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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54 ; CHECK-NEXT: %[[trunc2:.*]] = trunc i24 %[[insert0]] to i8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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55
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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56 %bsum0 = add i8 %b0, %b1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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57 %bsum1 = add i8 %bsum0, %b2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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58 ret i8 %bsum1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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59 ; CHECK: %[[sum0:.*]] = add i8 %[[trunc0]], %[[trunc1]]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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60 ; CHECK-NEXT: %[[sum1:.*]] = add i8 %[[sum0]], %[[trunc2]]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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61 ; CHECK-NEXT: ret i8 %[[sum1]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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62 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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63
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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64 define i64 @test2() {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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65 ; Test for various mixed sizes of integer loads and stores all getting
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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66 ; promoted.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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67 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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68 ; CHECK-LABEL: @test2(
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parents:
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69
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parents:
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70 entry:
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parents:
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71 %a = alloca [7 x i8]
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parents:
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72 ; CHECK-NOT: alloca
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parents:
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73
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74 %a0ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 0
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parents: 0
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75 %a1ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 1
afa8332a0e37 LLVM 3.8
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parents: 0
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76 %a2ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 2
afa8332a0e37 LLVM 3.8
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parents: 0
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77 %a3ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 0, i32 3
0
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parents:
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78
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79 ; CHECK-NOT: store
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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80 ; CHECK-NOT: load
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parents:
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81
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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82 %a0i16ptr = bitcast i8* %a0ptr to i16*
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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83 store i16 1, i16* %a0i16ptr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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84
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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85 store i8 1, i8* %a2ptr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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86 ; CHECK: %[[mask1:.*]] = and i40 undef, 4294967295
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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87 ; CHECK-NEXT: %[[insert1:.*]] = or i40 %[[mask1]], 4294967296
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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88
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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89 %a3i24ptr = bitcast i8* %a3ptr to i24*
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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90 store i24 1, i24* %a3i24ptr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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91 ; CHECK-NEXT: %[[mask2:.*]] = and i40 %[[insert1]], -4294967041
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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92 ; CHECK-NEXT: %[[insert2:.*]] = or i40 %[[mask2]], 256
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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93
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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94 %a2i40ptr = bitcast i8* %a2ptr to i40*
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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95 store i40 1, i40* %a2i40ptr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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96 ; CHECK-NEXT: %[[ext3:.*]] = zext i40 1 to i56
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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97 ; CHECK-NEXT: %[[mask3:.*]] = and i56 undef, -1099511627776
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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98 ; CHECK-NEXT: %[[insert3:.*]] = or i56 %[[mask3]], %[[ext3]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
99
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parents:
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100 ; CHECK-NOT: store
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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101 ; CHECK-NOT: load
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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102
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parents:
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103 %aiptr = bitcast [7 x i8]* %a to i56*
95
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parents: 0
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104 %ai = load i56, i56* %aiptr
0
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parents:
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105 %ret = zext i56 %ai to i64
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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106 ret i64 %ret
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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107 ; CHECK-NEXT: %[[ext4:.*]] = zext i16 1 to i56
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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108 ; CHECK-NEXT: %[[shift4:.*]] = shl i56 %[[ext4]], 40
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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109 ; CHECK-NEXT: %[[mask4:.*]] = and i56 %[[insert3]], 1099511627775
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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110 ; CHECK-NEXT: %[[insert4:.*]] = or i56 %[[mask4]], %[[shift4]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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111 ; CHECK-NEXT: %[[ret:.*]] = zext i56 %[[insert4]] to i64
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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112 ; CHECK-NEXT: ret i64 %[[ret]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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113 }
95
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parents: 0
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114
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parents: 0
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115 define i64 @PR14132(i1 %flag) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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116 ; CHECK-LABEL: @PR14132(
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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117 ; Here we form a PHI-node by promoting the pointer alloca first, and then in
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118 ; order to promote the other two allocas, we speculate the load of the
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119 ; now-phi-node-pointer. In doing so we end up loading a 64-bit value from an i8
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120 ; alloca. While this is a bit dubious, we were asserting on trying to
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parents: 0
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121 ; rewrite it. The trick is that the code using the value may carefully take
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parents: 0
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122 ; steps to only use the not-undef bits, and so we need to at least loosely
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parents: 0
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123 ; support this. This test is particularly interesting because how we handle
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124 ; a load of an i64 from an i8 alloca is dependent on endianness.
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diff changeset
125 entry:
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126 %a = alloca i64, align 8
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127 %b = alloca i8, align 8
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128 %ptr = alloca i64*, align 8
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129 ; CHECK-NOT: alloca
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130
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131 %ptr.cast = bitcast i64** %ptr to i8**
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132 store i64 0, i64* %a
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133 store i8 1, i8* %b
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134 store i64* %a, i64** %ptr
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parents: 0
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135 br i1 %flag, label %if.then, label %if.end
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diff changeset
136
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diff changeset
137 if.then:
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138 store i8* %b, i8** %ptr.cast
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139 br label %if.end
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140 ; CHECK-NOT: store
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parents: 0
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141 ; CHECK: %[[ext:.*]] = zext i8 1 to i64
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parents: 0
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142 ; CHECK: %[[shift:.*]] = shl i64 %[[ext]], 56
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parents: 0
diff changeset
143
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144 if.end:
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diff changeset
145 %tmp = load i64*, i64** %ptr
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146 %result = load i64, i64* %tmp
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diff changeset
147 ; CHECK-NOT: load
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148 ; CHECK: %[[result:.*]] = phi i64 [ %[[shift]], %if.then ], [ 0, %entry ]
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parents: 0
diff changeset
149
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150 ret i64 %result
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151 ; CHECK-NEXT: ret i64 %[[result]]
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152 }
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153
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154 declare void @f(i64 %x, i32 %y)
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155
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diff changeset
156 define void @test3() {
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157 ; CHECK-LABEL: @test3(
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158 ;
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159 ; This is a test that specifically exercises the big-endian lowering because it
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parents: 0
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160 ; ends up splitting a 64-bit integer into two smaller integers and has a number
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parents: 0
diff changeset
161 ; of tricky aspects (the i24 type) that make that hard. Historically, SROA
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parents: 0
diff changeset
162 ; would miscompile this by either dropping a most significant byte or least
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parents: 0
diff changeset
163 ; significant byte due to shrinking the [4,8) slice to an i24, or by failing to
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parents: 0
diff changeset
164 ; move the bytes around correctly.
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parents: 0
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165 ;
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166 ; The magical number 34494054408 is used because it has bits set in various
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parents: 0
diff changeset
167 ; bytes so that it is clear if those bytes fail to be propagated.
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168 ;
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169 ; If you're debugging this, rather than using the direct magical numbers, run
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parents: 0
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170 ; the IR through '-sroa -instcombine'. With '-instcombine' these will be
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parents: 0
diff changeset
171 ; constant folded, and if the i64 doesn't round-trip correctly, you've found
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parents: 0
diff changeset
172 ; a bug!
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173 ;
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174 entry:
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175 %a = alloca { i32, i24 }, align 4
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176 ; CHECK-NOT: alloca
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177
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178 %tmp0 = bitcast { i32, i24 }* %a to i64*
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179 store i64 34494054408, i64* %tmp0
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180 %tmp1 = load i64, i64* %tmp0, align 4
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181 %tmp2 = bitcast { i32, i24 }* %a to i32*
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182 %tmp3 = load i32, i32* %tmp2, align 4
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diff changeset
183 ; CHECK: %[[HI_EXT:.*]] = zext i32 134316040 to i64
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parents: 0
diff changeset
184 ; CHECK: %[[HI_INPUT:.*]] = and i64 undef, -4294967296
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parents: 0
diff changeset
185 ; CHECK: %[[HI_MERGE:.*]] = or i64 %[[HI_INPUT]], %[[HI_EXT]]
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parents: 0
diff changeset
186 ; CHECK: %[[LO_EXT:.*]] = zext i32 8 to i64
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parents: 0
diff changeset
187 ; CHECK: %[[LO_SHL:.*]] = shl i64 %[[LO_EXT]], 32
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parents: 0
diff changeset
188 ; CHECK: %[[LO_INPUT:.*]] = and i64 %[[HI_MERGE]], 4294967295
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parents: 0
diff changeset
189 ; CHECK: %[[LO_MERGE:.*]] = or i64 %[[LO_INPUT]], %[[LO_SHL]]
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parents: 0
diff changeset
190
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191 call void @f(i64 %tmp1, i32 %tmp3)
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192 ; CHECK: call void @f(i64 %[[LO_MERGE]], i32 8)
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parents: 0
diff changeset
193 ret void
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194 ; CHECK: ret void
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parents: 0
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195 }
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parents: 0
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196
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197 define void @test4() {
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198 ; CHECK-LABEL: @test4
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199 ;
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200 ; Much like @test3, this is specifically testing big-endian management of data.
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parents: 0
diff changeset
201 ; Also similarly, it uses constants with particular bits set to help track
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parents: 0
diff changeset
202 ; whether values are corrupted, and can be easily evaluated by running through
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parents: 0
diff changeset
203 ; -instcombine to see that the i64 round-trips.
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parents: 0
diff changeset
204 ;
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parents: 0
diff changeset
205 entry:
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parents: 0
diff changeset
206 %a = alloca { i32, i24 }, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
207 %a2 = alloca i64, align 4
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parents: 0
diff changeset
208 ; CHECK-NOT: alloca
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parents: 0
diff changeset
209
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parents: 0
diff changeset
210 store i64 34494054408, i64* %a2
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parents: 0
diff changeset
211 %tmp0 = bitcast { i32, i24 }* %a to i8*
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parents: 0
diff changeset
212 %tmp1 = bitcast i64* %a2 to i8*
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parents: 0
diff changeset
213 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp0, i8* %tmp1, i64 8, i32 4, i1 false)
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parents: 0
diff changeset
214 ; CHECK: %[[LO_SHR:.*]] = lshr i64 34494054408, 32
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parents: 0
diff changeset
215 ; CHECK: %[[LO_START:.*]] = trunc i64 %[[LO_SHR]] to i32
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parents: 0
diff changeset
216 ; CHECK: %[[HI_START:.*]] = trunc i64 34494054408 to i32
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parents: 0
diff changeset
217
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parents: 0
diff changeset
218 %tmp2 = bitcast { i32, i24 }* %a to i64*
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parents: 0
diff changeset
219 %tmp3 = load i64, i64* %tmp2, align 4
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parents: 0
diff changeset
220 %tmp4 = bitcast { i32, i24 }* %a to i32*
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parents: 0
diff changeset
221 %tmp5 = load i32, i32* %tmp4, align 4
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parents: 0
diff changeset
222 ; CHECK: %[[HI_EXT:.*]] = zext i32 %[[HI_START]] to i64
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parents: 0
diff changeset
223 ; CHECK: %[[HI_INPUT:.*]] = and i64 undef, -4294967296
afa8332a0e37 LLVM 3.8
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parents: 0
diff changeset
224 ; CHECK: %[[HI_MERGE:.*]] = or i64 %[[HI_INPUT]], %[[HI_EXT]]
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
225 ; CHECK: %[[LO_EXT:.*]] = zext i32 %[[LO_START]] to i64
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
226 ; CHECK: %[[LO_SHL:.*]] = shl i64 %[[LO_EXT]], 32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
227 ; CHECK: %[[LO_INPUT:.*]] = and i64 %[[HI_MERGE]], 4294967295
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
228 ; CHECK: %[[LO_MERGE:.*]] = or i64 %[[LO_INPUT]], %[[LO_SHL]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
229
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parents: 0
diff changeset
230 call void @f(i64 %tmp3, i32 %tmp5)
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parents: 0
diff changeset
231 ; CHECK: call void @f(i64 %[[LO_MERGE]], i32 %[[LO_START]])
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parents: 0
diff changeset
232 ret void
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parents: 0
diff changeset
233 ; CHECK: ret void
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parents: 0
diff changeset
234 }
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parents: 0
diff changeset
235
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parents: 0
diff changeset
236 declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)