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annotate utils/TableGen/PseudoLoweringEmitter.cpp @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 54457678186b
children 803732b1fca8
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1 //===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 #include "CodeGenInstruction.h"
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11 #include "CodeGenTarget.h"
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12 #include "llvm/ADT/IndexedMap.h"
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13 #include "llvm/ADT/SmallVector.h"
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14 #include "llvm/ADT/StringMap.h"
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15 #include "llvm/Support/Debug.h"
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16 #include "llvm/Support/ErrorHandling.h"
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17 #include "llvm/TableGen/Error.h"
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18 #include "llvm/TableGen/Record.h"
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19 #include "llvm/TableGen/TableGenBackend.h"
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20 #include <vector>
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21 using namespace llvm;
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22
77
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23 #define DEBUG_TYPE "pseudo-lowering"
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24
0
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25 namespace {
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26 class PseudoLoweringEmitter {
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27 struct OpData {
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28 enum MapKind { Operand, Imm, Reg };
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29 MapKind Kind;
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30 union {
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31 unsigned Operand; // Operand number mapped to.
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32 uint64_t Imm; // Integer immedate value.
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33 Record *Reg; // Physical register.
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34 } Data;
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35 };
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36 struct PseudoExpansion {
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37 CodeGenInstruction Source; // The source pseudo instruction definition.
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38 CodeGenInstruction Dest; // The destination instruction to lower to.
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39 IndexedMap<OpData> OperandMap;
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40
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41 PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
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42 IndexedMap<OpData> &m) :
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43 Source(s), Dest(d), OperandMap(m) {}
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44 };
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45
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46 RecordKeeper &Records;
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47
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48 // It's overkill to have an instance of the full CodeGenTarget object,
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49 // but it loads everything on demand, not in the constructor, so it's
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50 // lightweight in performance, so it works out OK.
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51 CodeGenTarget Target;
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52
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53 SmallVector<PseudoExpansion, 64> Expansions;
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54
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55 unsigned addDagOperandMapping(Record *Rec, DagInit *Dag,
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56 CodeGenInstruction &Insn,
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57 IndexedMap<OpData> &OperandMap,
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58 unsigned BaseIdx);
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59 void evaluateExpansion(Record *Pseudo);
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60 void emitLoweringEmitter(raw_ostream &o);
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61 public:
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62 PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}
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63
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64 /// run - Output the pseudo-lowerings.
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65 void run(raw_ostream &o);
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66 };
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67 } // End anonymous namespace
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68
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69 // FIXME: This pass currently can only expand a pseudo to a single instruction.
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70 // The pseudo expansion really should take a list of dags, not just
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71 // a single dag, so we can do fancier things.
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72
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73 unsigned PseudoLoweringEmitter::
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74 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
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75 IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
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76 unsigned OpsAdded = 0;
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77 for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
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78 if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
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79 // Physical register reference. Explicit check for the special case
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80 // "zero_reg" definition.
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81 if (DI->getDef()->isSubClassOf("Register") ||
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82 DI->getDef()->getName() == "zero_reg") {
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83 OperandMap[BaseIdx + i].Kind = OpData::Reg;
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84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
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85 ++OpsAdded;
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86 continue;
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87 }
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88
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89 // Normal operands should always have the same type, or we have a
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90 // problem.
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91 // FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
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92 assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
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93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
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94 PrintFatalError(Rec->getLoc(),
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95 "Pseudo operand type '" + DI->getDef()->getName() +
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96 "' does not match expansion operand type '" +
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97 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
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98 // Source operand maps to destination operand. The Data element
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99 // will be filled in later, just set the Kind for now. Do it
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100 // for each corresponding MachineInstr operand, not just the first.
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101 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
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102 OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
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103 OpsAdded += Insn.Operands[i].MINumOperands;
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104 } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
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105 OperandMap[BaseIdx + i].Kind = OpData::Imm;
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106 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
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107 ++OpsAdded;
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108 } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
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109 // Just add the operands recursively. This is almost certainly
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110 // a constant value for a complex operand (> 1 MI operand).
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111 unsigned NewOps =
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112 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
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113 OpsAdded += NewOps;
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114 // Since we added more than one, we also need to adjust the base.
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115 BaseIdx += NewOps - 1;
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116 } else
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117 llvm_unreachable("Unhandled pseudo-expansion argument type!");
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118 }
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119 return OpsAdded;
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120 }
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121
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122 void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
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123 DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");
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124
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125 // Validate that the result pattern has the corrent number and types
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126 // of arguments for the instruction it references.
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127 DagInit *Dag = Rec->getValueAsDag("ResultInst");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
128 assert(Dag && "Missing result instruction in pseudo expansion!");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
129 DEBUG(dbgs() << " Result: " << *Dag << "\n");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
130
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
131 DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
132 if (!OpDef)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
133 PrintFatalError(Rec->getLoc(), Rec->getName() +
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
134 " has unexpected operator type!");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
135 Record *Operator = OpDef->getDef();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
136 if (!Operator->isSubClassOf("Instruction"))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 "' is not an instruction!");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
139
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
140 CodeGenInstruction Insn(Operator);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
141
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 if (Insn.isCodeGenOnly || Insn.isPseudo)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 "' cannot be another pseudo instruction!");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
145
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 if (Insn.Operands.size() != Dag->getNumArgs())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
148 "' operand count mismatch");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
149
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
150 unsigned NumMIOperands = 0;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 NumMIOperands += Insn.Operands[i].MINumOperands;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 IndexedMap<OpData> OperandMap;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 OperandMap.grow(NumMIOperands);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
155
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
157
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
158 // If there are more operands that weren't in the DAG, they have to
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 // be operands that have default values, or we have an error. Currently,
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
160 // Operands that are a subclass of OperandWithDefaultOp have default values.
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
161
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 // Validate that each result pattern argument has a matching (by name)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 // argument in the source instruction, in either the (outs) or (ins) list.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
164 // Also check that the type of the arguments match.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 //
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 // Record the mapping of the source to result arguments for use by
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 // the lowering emitter.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 CodeGenInstruction SourceInsn(Rec);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 StringMap<unsigned> SourceOperands;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
171 SourceOperands[SourceInsn.Operands[i].Name] = i;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
172
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 DEBUG(dbgs() << " Operand mapping:\n");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 // We've already handled constant values. Just map instruction operands
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 // here.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
177 if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
178 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 StringMap<unsigned>::iterator SourceOp =
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 SourceOperands.find(Dag->getArgName(i));
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 if (SourceOp == SourceOperands.end())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 PrintFatalError(Rec->getLoc(),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 "Pseudo output operand '" + Dag->getArgName(i) +
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 "' has no matching source operand.");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 // Map the source operand to the destination operand index for each
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 // MachineInstr operand.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
188 OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 SourceOp->getValue();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
190
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << i << "\n");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
193
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
194 Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap));
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
195 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
196
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
198 // Emit file header.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
199 emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
200
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
201 o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
202 << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
203 << " const MachineInstr *MI) {\n";
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
204
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
205 if (!Expansions.empty()) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
206 o << " switch (MI->getOpcode()) {\n"
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
207 << " default: return false;\n";
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
208 for (auto &Expansion : Expansions) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
209 CodeGenInstruction &Source = Expansion.Source;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
210 CodeGenInstruction &Dest = Expansion.Dest;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
211 o << " case " << Source.Namespace << "::"
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
212 << Source.TheDef->getName() << ": {\n"
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
213 << " MCInst TmpInst;\n"
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
214 << " MCOperand MCOp;\n"
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
215 << " TmpInst.setOpcode(" << Dest.Namespace << "::"
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
216 << Dest.TheDef->getName() << ");\n";
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
217
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
218 // Copy the operands from the source instruction.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
219 // FIXME: Instruction operands with defaults values (predicates and cc_out
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
220 // in ARM, for example shouldn't need explicit values in the
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
221 // expansion DAG.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
222 unsigned MIOpNo = 0;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
223 for (const auto &DestOperand : Dest.Operands) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
224 o << " // Operand: " << DestOperand.Name << "\n";
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
225 for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
226 switch (Expansion.OperandMap[MIOpNo + i].Kind) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
227 case OpData::Operand:
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
228 o << " lowerOperand(MI->getOperand("
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
229 << Source.Operands[Expansion.OperandMap[MIOpNo].Data
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
230 .Operand].MIOperandNo + i
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
231 << "), MCOp);\n"
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
232 << " TmpInst.addOperand(MCOp);\n";
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
233 break;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
234 case OpData::Imm:
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
235 o << " TmpInst.addOperand(MCOperand::createImm("
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
236 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
237 break;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
238 case OpData::Reg: {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
239 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
240 o << " TmpInst.addOperand(MCOperand::createReg(";
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
241 // "zero_reg" is special.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
242 if (Reg->getName() == "zero_reg")
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
243 o << "0";
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
244 else
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
245 o << Reg->getValueAsString("Namespace") << "::"
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
246 << Reg->getName();
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
247 o << "));\n";
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
248 break;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
249 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
250 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 }
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
252 MIOpNo += DestOperand.MINumOperands;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 }
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
254 if (Dest.Operands.isVariadic) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
255 MIOpNo = Source.Operands.size() + 1;
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256 o << " // variable_ops\n";
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257 o << " for (unsigned i = " << MIOpNo
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258 << ", e = MI->getNumOperands(); i != e; ++i)\n"
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259 << " if (lowerOperand(MI->getOperand(i), MCOp))\n"
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260 << " TmpInst.addOperand(MCOp);\n";
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261 }
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262 o << " EmitToStreamer(OutStreamer, TmpInst);\n"
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263 << " break;\n"
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264 << " }\n";
0
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265 }
77
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266 o << " }\n return true;";
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267 } else
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268 o << " return false;";
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269
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270 o << "\n}\n\n";
0
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271 }
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272
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273 void PseudoLoweringEmitter::run(raw_ostream &o) {
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274 Record *ExpansionClass = Records.getClass("PseudoInstExpansion");
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275 Record *InstructionClass = Records.getClass("Instruction");
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276 assert(ExpansionClass && "PseudoInstExpansion class definition missing!");
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277 assert(InstructionClass && "Instruction class definition missing!");
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278
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279 std::vector<Record*> Insts;
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280 for (const auto &D : Records.getDefs()) {
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281 if (D.second->isSubClassOf(ExpansionClass) &&
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282 D.second->isSubClassOf(InstructionClass))
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283 Insts.push_back(D.second.get());
0
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284 }
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285
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286 // Process the pseudo expansion definitions, validating them as we do so.
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287 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
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288 evaluateExpansion(Insts[i]);
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289
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290 // Generate expansion code to lower the pseudo to an MCInst of the real
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291 // instruction.
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292 emitLoweringEmitter(o);
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293 }
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294
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295 namespace llvm {
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296
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297 void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
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298 PseudoLoweringEmitter(RK).run(OS);
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299 }
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300
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301 } // End llvm namespace