CbC/CbC_llvm: lib/Target/Hexagon/HexagonSplitDouble.cpp annotate

annotate lib/Target/Hexagon/HexagonSplitDouble.cpp @ 147:c2174574ed3a

LLVM 10

author	Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date	Wed, 14 Aug 2019 16:55:33 +0900
parents	3a76565eade5
children

rev	line source
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	1 //===- HexagonSplitDouble.cpp ---------------------------------------------===//
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	2 //
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	4 // See https://llvm.org/LICENSE.txt for license information.
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	6 //
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	7 //===----------------------------------------------------------------------===//
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	8
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	9 #define DEBUG_TYPE "hsdr"
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	10
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	11 #include "HexagonInstrInfo.h"
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	12 #include "HexagonRegisterInfo.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	13 #include "HexagonSubtarget.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	14 #include "llvm/ADT/BitVector.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	15 #include "llvm/ADT/STLExtras.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	16 #include "llvm/ADT/SmallVector.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	17 #include "llvm/ADT/StringRef.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	18 #include "llvm/CodeGen/MachineBasicBlock.h"
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	19 #include "llvm/CodeGen/MachineFunction.h"
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	20 #include "llvm/CodeGen/MachineFunctionPass.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	21 #include "llvm/CodeGen/MachineInstr.h"
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	22 #include "llvm/CodeGen/MachineInstrBuilder.h"
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	23 #include "llvm/CodeGen/MachineLoopInfo.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	24 #include "llvm/CodeGen/MachineMemOperand.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	25 #include "llvm/CodeGen/MachineOperand.h"
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	26 #include "llvm/CodeGen/MachineRegisterInfo.h"
134 3a76565eade5 update 5.0.1 mir3636 parents: 121 diff changeset	27 #include "llvm/CodeGen/TargetRegisterInfo.h"
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	28 #include "llvm/Config/llvm-config.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	29 #include "llvm/IR/DebugLoc.h"
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	30 #include "llvm/Pass.h"
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	31 #include "llvm/Support/CommandLine.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	32 #include "llvm/Support/Compiler.h"
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	33 #include "llvm/Support/Debug.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	34 #include "llvm/Support/ErrorHandling.h"
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	35 #include "llvm/Support/raw_ostream.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	36 #include <algorithm>
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	37 #include <cassert>
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	38 #include <cstdint>
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	39 #include <limits>
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	40 #include <map>
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	41 #include <set>
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	42 #include <utility>
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	43 #include <vector>
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	44
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	45 using namespace llvm;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	46
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	47 namespace llvm {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	48
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	49 FunctionPass *createHexagonSplitDoubleRegs();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	50 void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	51
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	52 } // end namespace llvm
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	53
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	54 static cl::opt<int> MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1),
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	55 cl::desc("Maximum number of split partitions"));
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	56 static cl::opt<bool> MemRefsFixed("hsdr-no-mem", cl::Hidden, cl::init(true),
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	57 cl::desc("Do not split loads or stores"));
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	58 static cl::opt<bool> SplitAll("hsdr-split-all", cl::Hidden, cl::init(false),
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	59 cl::desc("Split all partitions"));
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	60
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	61 namespace {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	62
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	63 class HexagonSplitDoubleRegs : public MachineFunctionPass {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	64 public:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	65 static char ID;
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	66
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	67 HexagonSplitDoubleRegs() : MachineFunctionPass(ID) {}
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	68
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	69 StringRef getPassName() const override {
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	70 return "Hexagon Split Double Registers";
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	71 }
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	72
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	73 void getAnalysisUsage(AnalysisUsage &AU) const override {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	74 AU.addRequired<MachineLoopInfo>();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	75 AU.addPreserved<MachineLoopInfo>();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	76 MachineFunctionPass::getAnalysisUsage(AU);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	77 }
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	78
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	79 bool runOnMachineFunction(MachineFunction &MF) override;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	80
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	81 private:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	82 static const TargetRegisterClass *const DoubleRC;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	83
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	84 const HexagonRegisterInfo *TRI = nullptr;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	85 const HexagonInstrInfo *TII = nullptr;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	86 const MachineLoopInfo *MLI;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	87 MachineRegisterInfo *MRI;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	88
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	89 using USet = std::set<unsigned>;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	90 using UUSetMap = std::map<unsigned, USet>;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	91 using UUPair = std::pair<unsigned, unsigned>;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	92 using UUPairMap = std::map<unsigned, UUPair>;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	93 using LoopRegMap = std::map<const MachineLoop *, USet>;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	94
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	95 bool isInduction(unsigned Reg, LoopRegMap &IRM) const;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	96 bool isVolatileInstr(const MachineInstr *MI) const;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	97 bool isFixedInstr(const MachineInstr *MI) const;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	98 void partitionRegisters(UUSetMap &P2Rs);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	99 int32_t profit(const MachineInstr *MI) const;
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	100 int32_t profit(unsigned Reg) const;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	101 bool isProfitable(const USet &Part, LoopRegMap &IRM) const;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	102
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	103 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	104 void collectIndRegs(LoopRegMap &IRM);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	105
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	106 void createHalfInstr(unsigned Opc, MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	107 const UUPairMap &PairMap, unsigned SubR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	108 void splitMemRef(MachineInstr *MI, const UUPairMap &PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	109 void splitImmediate(MachineInstr *MI, const UUPairMap &PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	110 void splitCombine(MachineInstr *MI, const UUPairMap &PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	111 void splitExt(MachineInstr *MI, const UUPairMap &PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	112 void splitShift(MachineInstr *MI, const UUPairMap &PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	113 void splitAslOr(MachineInstr *MI, const UUPairMap &PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	114 bool splitInstr(MachineInstr *MI, const UUPairMap &PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	115 void replaceSubregUses(MachineInstr *MI, const UUPairMap &PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	116 void collapseRegPairs(MachineInstr *MI, const UUPairMap &PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	117 bool splitPartition(const USet &Part);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	118
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	119 static int Counter;
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	120
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	121 static void dump_partition(raw_ostream&, const USet&,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	122 const TargetRegisterInfo&);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	123 };
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	124
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	125 } // end anonymous namespace
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	126
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	127 char HexagonSplitDoubleRegs::ID;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	128 int HexagonSplitDoubleRegs::Counter = 0;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	129 const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC =
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	130 &Hexagon::DoubleRegsRegClass;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	131
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	132 INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	133 "Hexagon Split Double Registers", false, false)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	134
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	135 #if !defined(NDEBUG) \|\| defined(LLVM_ENABLE_DUMP)
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	136 LLVM_DUMP_METHOD void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	137 const USet &Part, const TargetRegisterInfo &TRI) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	138 dbgs() << '{';
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	139 for (auto I : Part)
134 3a76565eade5 update 5.0.1 mir3636 parents: 121 diff changeset	140 dbgs() << ' ' << printReg(I, &TRI);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	141 dbgs() << " }";
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	142 }
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	143 #endif
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	144
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	145 bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	146 for (auto I : IRM) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	147 const USet &Rs = I.second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	148 if (Rs.find(Reg) != Rs.end())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	149 return true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	150 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	151 return false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	152 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	153
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	154 bool HexagonSplitDoubleRegs::isVolatileInstr(const MachineInstr *MI) const {
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	155 for (auto &MO : MI->memoperands())
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	156 if (MO->isVolatile() \|\| MO->isAtomic())
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	157 return true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	158 return false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	159 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	160
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	161 bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	162 if (MI->mayLoad() \|\| MI->mayStore())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	163 if (MemRefsFixed \|\| isVolatileInstr(MI))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	164 return true;
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	165 if (MI->isDebugInstr())
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	166 return false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	167
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	168 unsigned Opc = MI->getOpcode();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	169 switch (Opc) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	170 default:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	171 return true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	172
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	173 case TargetOpcode::PHI:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	174 case TargetOpcode::COPY:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	175 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	176
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	177 case Hexagon::L2_loadrd_io:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	178 // Not handling stack stores (only reg-based addresses).
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	179 if (MI->getOperand(1).isReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	180 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	181 return true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	182 case Hexagon::S2_storerd_io:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	183 // Not handling stack stores (only reg-based addresses).
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	184 if (MI->getOperand(0).isReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	185 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	186 return true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	187 case Hexagon::L2_loadrd_pi:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	188 case Hexagon::S2_storerd_pi:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	189
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	190 case Hexagon::A2_tfrpi:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	191 case Hexagon::A2_combineii:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	192 case Hexagon::A4_combineir:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	193 case Hexagon::A4_combineii:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	194 case Hexagon::A4_combineri:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	195 case Hexagon::A2_combinew:
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	196 case Hexagon::CONST64:
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	197
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	198 case Hexagon::A2_sxtw:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	199
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	200 case Hexagon::A2_andp:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	201 case Hexagon::A2_orp:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	202 case Hexagon::A2_xorp:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	203 case Hexagon::S2_asl_i_p_or:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	204 case Hexagon::S2_asl_i_p:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	205 case Hexagon::S2_asr_i_p:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	206 case Hexagon::S2_lsr_i_p:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	207 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	208 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	209
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	210 for (auto &Op : MI->operands()) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	211 if (!Op.isReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	212 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	213 unsigned R = Op.getReg();
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	214 if (!Register::isVirtualRegister(R))
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	215 return true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	216 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	217 return false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	218 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	219
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	220 void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	221 using UUMap = std::map<unsigned, unsigned>;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	222 using UVect = std::vector<unsigned>;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	223
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	224 unsigned NumRegs = MRI->getNumVirtRegs();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	225 BitVector DoubleRegs(NumRegs);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	226 for (unsigned i = 0; i < NumRegs; ++i) {
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	227 unsigned R = Register::index2VirtReg(i);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	228 if (MRI->getRegClass(R) == DoubleRC)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	229 DoubleRegs.set(i);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	230 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	231
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	232 BitVector FixedRegs(NumRegs);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	233 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	234 unsigned R = Register::index2VirtReg(x);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	235 MachineInstr *DefI = MRI->getVRegDef(R);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	236 // In some cases a register may exist, but never be defined or used.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	237 // It should never appear anywhere, but mark it as "fixed", just to be
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	238 // safe.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	239 if (!DefI \|\| isFixedInstr(DefI))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	240 FixedRegs.set(x);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	241 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	242
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	243 UUSetMap AssocMap;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	244 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	245 if (FixedRegs[x])
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	246 continue;
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	247 unsigned R = Register::index2VirtReg(x);
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	248 LLVM_DEBUG(dbgs() << printReg(R, TRI) << " ~~");
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	249 USet &Asc = AssocMap[R];
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	250 for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	251 U != Z; ++U) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	252 MachineOperand &Op = *U;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	253 MachineInstr *UseI = Op.getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	254 if (isFixedInstr(UseI))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	255 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	256 for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	257 MachineOperand &MO = UseI->getOperand(i);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	258 // Skip non-registers or registers with subregisters.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	259 if (&MO == &Op \|\| !MO.isReg() \|\| MO.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	260 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	261 unsigned T = MO.getReg();
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	262 if (!Register::isVirtualRegister(T)) {
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	263 FixedRegs.set(x);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	264 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	265 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	266 if (MRI->getRegClass(T) != DoubleRC)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	267 continue;
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	268 unsigned u = Register::virtReg2Index(T);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	269 if (FixedRegs[u])
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	270 continue;
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	271 LLVM_DEBUG(dbgs() << ' ' << printReg(T, TRI));
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	272 Asc.insert(T);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	273 // Make it symmetric.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	274 AssocMap[T].insert(R);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	275 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	276 }
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	277 LLVM_DEBUG(dbgs() << '\n');
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	278 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	279
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	280 UUMap R2P;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	281 unsigned NextP = 1;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	282 USet Visited;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	283 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	284 unsigned R = Register::index2VirtReg(x);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	285 if (Visited.count(R))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	286 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	287 // Create a new partition for R.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	288 unsigned ThisP = FixedRegs[x] ? 0 : NextP++;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	289 UVect WorkQ;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	290 WorkQ.push_back(R);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	291 for (unsigned i = 0; i < WorkQ.size(); ++i) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	292 unsigned T = WorkQ[i];
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	293 if (Visited.count(T))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	294 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	295 R2P[T] = ThisP;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	296 Visited.insert(T);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	297 // Add all registers associated with T.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	298 USet &Asc = AssocMap[T];
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	299 for (USet::iterator J = Asc.begin(), F = Asc.end(); J != F; ++J)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	300 WorkQ.push_back(*J);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	301 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	302 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	303
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	304 for (auto I : R2P)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	305 P2Rs[I.second].insert(I.first);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	306 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	307
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	308 static inline int32_t profitImm(unsigned Imm) {
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	309 int32_t P = 0;
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	310 if (Imm == 0 \|\| Imm == 0xFFFFFFFF)
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	311 P += 10;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	312 return P;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	313 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	314
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	315 int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	316 unsigned ImmX = 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	317 unsigned Opc = MI->getOpcode();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	318 switch (Opc) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	319 case TargetOpcode::PHI:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	320 for (const auto &Op : MI->operands())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	321 if (!Op.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	322 return 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	323 return 10;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	324 case TargetOpcode::COPY:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	325 if (MI->getOperand(1).getSubReg() != 0)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	326 return 10;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	327 return 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	328
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	329 case Hexagon::L2_loadrd_io:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	330 case Hexagon::S2_storerd_io:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	331 return -1;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	332 case Hexagon::L2_loadrd_pi:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	333 case Hexagon::S2_storerd_pi:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	334 return 2;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	335
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	336 case Hexagon::A2_tfrpi:
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	337 case Hexagon::CONST64: {
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	338 uint64_t D = MI->getOperand(1).getImm();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	339 unsigned Lo = D & 0xFFFFFFFFULL;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	340 unsigned Hi = D >> 32;
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	341 return profitImm(Lo) + profitImm(Hi);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	342 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	343 case Hexagon::A2_combineii:
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	344 case Hexagon::A4_combineii: {
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	345 const MachineOperand &Op1 = MI->getOperand(1);
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	346 const MachineOperand &Op2 = MI->getOperand(2);
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	347 int32_t Prof1 = Op1.isImm() ? profitImm(Op1.getImm()) : 0;
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	348 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0;
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	349 return Prof1 + Prof2;
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	350 }
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	351 case Hexagon::A4_combineri:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	352 ImmX++;
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	353 // Fall through into A4_combineir.
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	354 LLVM_FALLTHROUGH;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	355 case Hexagon::A4_combineir: {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	356 ImmX++;
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	357 const MachineOperand &OpX = MI->getOperand(ImmX);
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	358 if (OpX.isImm()) {
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	359 int64_t V = OpX.getImm();
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	360 if (V == 0 \|\| V == -1)
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	361 return 10;
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	362 }
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	363 // Fall through into A2_combinew.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	364 LLVM_FALLTHROUGH;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	365 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	366 case Hexagon::A2_combinew:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	367 return 2;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	368
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	369 case Hexagon::A2_sxtw:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	370 return 3;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	371
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	372 case Hexagon::A2_andp:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	373 case Hexagon::A2_orp:
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	374 case Hexagon::A2_xorp: {
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	375 unsigned Rs = MI->getOperand(1).getReg();
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	376 unsigned Rt = MI->getOperand(2).getReg();
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	377 return profit(Rs) + profit(Rt);
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	378 }
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	379
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	380 case Hexagon::S2_asl_i_p_or: {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	381 unsigned S = MI->getOperand(3).getImm();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	382 if (S == 0 \|\| S == 32)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	383 return 10;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	384 return -1;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	385 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	386 case Hexagon::S2_asl_i_p:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	387 case Hexagon::S2_asr_i_p:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	388 case Hexagon::S2_lsr_i_p:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	389 unsigned S = MI->getOperand(2).getImm();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	390 if (S == 0 \|\| S == 32)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	391 return 10;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	392 if (S == 16)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	393 return 5;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	394 if (S == 48)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	395 return 7;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	396 return -10;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	397 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	398
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	399 return 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	400 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	401
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	402 int32_t HexagonSplitDoubleRegs::profit(unsigned Reg) const {
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	403 assert(Register::isVirtualRegister(Reg));
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	404
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	405 const MachineInstr *DefI = MRI->getVRegDef(Reg);
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	406 switch (DefI->getOpcode()) {
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	407 case Hexagon::A2_tfrpi:
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	408 case Hexagon::CONST64:
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	409 case Hexagon::A2_combineii:
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	410 case Hexagon::A4_combineii:
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	411 case Hexagon::A4_combineri:
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	412 case Hexagon::A4_combineir:
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	413 case Hexagon::A2_combinew:
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	414 return profit(DefI);
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	415 default:
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	416 break;
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	417 }
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	418 return 0;
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	419 }
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	420
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	421 bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	422 const {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	423 unsigned FixedNum = 0, LoopPhiNum = 0;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	424 int32_t TotalP = 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	425
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	426 for (unsigned DR : Part) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	427 MachineInstr *DefI = MRI->getVRegDef(DR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	428 int32_t P = profit(DefI);
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	429 if (P == std::numeric_limits<int>::min())
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	430 return false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	431 TotalP += P;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	432 // Reduce the profitability of splitting induction registers.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	433 if (isInduction(DR, IRM))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	434 TotalP -= 30;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	435
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	436 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	437 U != W; ++U) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	438 MachineInstr *UseI = U->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	439 if (isFixedInstr(UseI)) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	440 FixedNum++;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	441 // Calculate the cost of generating REG_SEQUENCE instructions.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	442 for (auto &Op : UseI->operands()) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	443 if (Op.isReg() && Part.count(Op.getReg()))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	444 if (Op.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	445 TotalP -= 2;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	446 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	447 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	448 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	449 // If a register from this partition is used in a fixed instruction,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	450 // and there is also a register in this partition that is used in
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	451 // a loop phi node, then decrease the splitting profit as this can
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	452 // confuse the modulo scheduler.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	453 if (UseI->isPHI()) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	454 const MachineBasicBlock *PB = UseI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	455 const MachineLoop *L = MLI->getLoopFor(PB);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	456 if (L && L->getHeader() == PB)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	457 LoopPhiNum++;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	458 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	459 // Splittable instruction.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	460 int32_t P = profit(UseI);
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	461 if (P == std::numeric_limits<int>::min())
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	462 return false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	463 TotalP += P;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	464 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	465 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	466
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	467 if (FixedNum > 0 && LoopPhiNum > 0)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	468 TotalP -= 20*LoopPhiNum;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	469
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	470 LLVM_DEBUG(dbgs() << "Partition profit: " << TotalP << '\n');
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	471 if (SplitAll)
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	472 return true;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	473 return TotalP > 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	474 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	475
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	476 void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	477 USet &Rs) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	478 const MachineBasicBlock *HB = L->getHeader();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	479 const MachineBasicBlock *LB = L->getLoopLatch();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	480 if (!HB \|\| !LB)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	481 return;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	482
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	483 // Examine the latch branch. Expect it to be a conditional branch to
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	484 // the header (either "br-cond header" or "br-cond exit; br header").
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	485 MachineBasicBlock TB = nullptr, FB = nullptr;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	486 MachineBasicBlock TmpLB = const_cast<MachineBasicBlock>(LB);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	487 SmallVector<MachineOperand,2> Cond;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	488 bool BadLB = TII->analyzeBranch(*TmpLB, TB, FB, Cond, false);
1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	489 // Only analyzable conditional branches. HII::analyzeBranch will put
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	490 // the branch opcode as the first element of Cond, and the predicate
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	491 // operand as the second.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	492 if (BadLB \|\| Cond.size() != 2)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	493 return;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	494 // Only simple jump-conditional (with or without negation).
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	495 if (!TII->PredOpcodeHasJMP_c(Cond[0].getImm()))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	496 return;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	497 // Must go to the header.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	498 if (TB != HB && FB != HB)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	499 return;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	500 assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch");
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	501 // Expect a predicate register.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	502 unsigned PR = Cond[1].getReg();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	503 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	504
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	505 // Get the registers on which the loop controlling compare instruction
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	506 // depends.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	507 unsigned CmpR1 = 0, CmpR2 = 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	508 const MachineInstr *CmpI = MRI->getVRegDef(PR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	509 while (CmpI->getOpcode() == Hexagon::C2_not)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	510 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	511
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	512 int Mask = 0, Val = 0;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	513 bool OkCI = TII->analyzeCompare(*CmpI, CmpR1, CmpR2, Mask, Val);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	514 if (!OkCI)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	515 return;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	516 // Eliminate non-double input registers.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	517 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	518 CmpR1 = 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	519 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	520 CmpR2 = 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	521 if (!CmpR1 && !CmpR2)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	522 return;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	523
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	524 // Now examine the top of the loop: the phi nodes that could poten-
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	525 // tially define loop induction registers. The registers defined by
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	526 // such a phi node would be used in a 64-bit add, which then would
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	527 // be used in the loop compare instruction.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	528
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	529 // Get the set of all double registers defined by phi nodes in the
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	530 // loop header.
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	531 using UVect = std::vector<unsigned>;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	532
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	533 UVect DP;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	534 for (auto &MI : *HB) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	535 if (!MI.isPHI())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	536 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	537 const MachineOperand &MD = MI.getOperand(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	538 unsigned R = MD.getReg();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	539 if (MRI->getRegClass(R) == DoubleRC)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	540 DP.push_back(R);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	541 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	542 if (DP.empty())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	543 return;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	544
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	545 auto NoIndOp = [this, CmpR1, CmpR2] (unsigned R) -> bool {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	546 for (auto I = MRI->use_nodbg_begin(R), E = MRI->use_nodbg_end();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	547 I != E; ++I) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	548 const MachineInstr *UseI = I->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	549 if (UseI->getOpcode() != Hexagon::A2_addp)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	550 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	551 // Get the output from the add. If it is one of the inputs to the
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	552 // loop-controlling compare instruction, then R is likely an induc-
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	553 // tion register.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	554 unsigned T = UseI->getOperand(0).getReg();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	555 if (T == CmpR1 \|\| T == CmpR2)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	556 return false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	557 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	558 return true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	559 };
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	560 UVect::iterator End = llvm::remove_if(DP, NoIndOp);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	561 Rs.insert(DP.begin(), End);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	562 Rs.insert(CmpR1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	563 Rs.insert(CmpR2);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	564
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	565 LLVM_DEBUG({
134 3a76565eade5 update 5.0.1 mir3636 parents: 121 diff changeset	566 dbgs() << "For loop at " << printMBBReference(*HB) << " ind regs: ";
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	567 dump_partition(dbgs(), Rs, *TRI);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	568 dbgs() << '\n';
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	569 });
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	570 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	571
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	572 void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	573 using LoopVector = std::vector<MachineLoop *>;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	574
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	575 LoopVector WorkQ;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	576
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	577 for (auto I : *MLI)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	578 WorkQ.push_back(I);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	579 for (unsigned i = 0; i < WorkQ.size(); ++i) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	580 for (auto I : *WorkQ[i])
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	581 WorkQ.push_back(I);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	582 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	583
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	584 USet Rs;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	585 for (unsigned i = 0, n = WorkQ.size(); i < n; ++i) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	586 MachineLoop *L = WorkQ[i];
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	587 Rs.clear();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	588 collectIndRegsForLoop(L, Rs);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	589 if (!Rs.empty())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	590 IRM.insert(std::make_pair(L, Rs));
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	591 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	592 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	593
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	594 void HexagonSplitDoubleRegs::createHalfInstr(unsigned Opc, MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	595 const UUPairMap &PairMap, unsigned SubR) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	596 MachineBasicBlock &B = *MI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	597 DebugLoc DL = MI->getDebugLoc();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	598 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc));
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	599
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	600 for (auto &Op : MI->operands()) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	601 if (!Op.isReg()) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	602 NewI->addOperand(Op);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	603 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	604 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	605 // For register operands, set the subregister.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	606 unsigned R = Op.getReg();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	607 unsigned SR = Op.getSubReg();
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	608 bool isVirtReg = Register::isVirtualRegister(R);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	609 bool isKill = Op.isKill();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	610 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	611 isKill = false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	612 UUPairMap::const_iterator F = PairMap.find(R);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	613 if (F == PairMap.end()) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	614 SR = SubR;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	615 } else {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	616 const UUPair &P = F->second;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	617 R = (SubR == Hexagon::isub_lo) ? P.first : P.second;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	618 SR = 0;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	619 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	620 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	621 auto CO = MachineOperand::CreateReg(R, Op.isDef(), Op.isImplicit(), isKill,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	622 Op.isDead(), Op.isUndef(), Op.isEarlyClobber(), SR, Op.isDebug(),
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	623 Op.isInternalRead());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	624 NewI->addOperand(CO);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	625 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	626 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	627
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	628 void HexagonSplitDoubleRegs::splitMemRef(MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	629 const UUPairMap &PairMap) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	630 bool Load = MI->mayLoad();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	631 unsigned OrigOpc = MI->getOpcode();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	632 bool PostInc = (OrigOpc == Hexagon::L2_loadrd_pi \|\|
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	633 OrigOpc == Hexagon::S2_storerd_pi);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	634 MachineInstr LowI, HighI;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	635 MachineBasicBlock &B = *MI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	636 DebugLoc DL = MI->getDebugLoc();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	637
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	638 // Index of the base-address-register operand.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	639 unsigned AdrX = PostInc ? (Load ? 2 : 1)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	640 : (Load ? 1 : 0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	641 MachineOperand &AdrOp = MI->getOperand(AdrX);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	642 unsigned RSA = getRegState(AdrOp);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	643 MachineOperand &ValOp = Load ? MI->getOperand(0)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	644 : (PostInc ? MI->getOperand(3)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	645 : MI->getOperand(2));
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	646 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	647 assert(F != PairMap.end());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	648
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	649 if (Load) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	650 const UUPair &P = F->second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	651 int64_t Off = PostInc ? 0 : MI->getOperand(2).getImm();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	652 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	654 .addImm(Off);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	655 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	657 .addImm(Off+4);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	658 } else {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	659 const UUPair &P = F->second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	660 int64_t Off = PostInc ? 0 : MI->getOperand(1).getImm();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	661 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	663 .addImm(Off)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	664 .addReg(P.first);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	665 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	667 .addImm(Off+4)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	668 .addReg(P.second);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	669 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	670
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	671 if (PostInc) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	672 // Create the increment of the address register.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	673 int64_t Inc = Load ? MI->getOperand(3).getImm()
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	674 : MI->getOperand(2).getImm();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	675 MachineOperand &UpdOp = Load ? MI->getOperand(1) : MI->getOperand(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	676 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	677 unsigned NewR = MRI->createVirtualRegister(RC);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	678 assert(!UpdOp.getSubReg() && "Def operand with subreg");
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	679 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	680 .addReg(AdrOp.getReg(), RSA)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	681 .addImm(Inc);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	682 MRI->replaceRegWith(UpdOp.getReg(), NewR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	683 // The original instruction will be deleted later.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	684 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	685
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	686 // Generate a new pair of memory-operands.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	687 MachineFunction &MF = *B.getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	688 for (auto &MO : MI->memoperands()) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	689 const MachinePointerInfo &Ptr = MO->getPointerInfo();
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	690 MachineMemOperand::Flags F = MO->getFlags();
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	691 int A = MO->getAlignment();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	692
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	693 auto Tmp1 = MF.getMachineMemOperand(Ptr, F, 4/size*/, A);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	694 LowI->addMemOperand(MF, Tmp1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	695 auto Tmp2 = MF.getMachineMemOperand(Ptr, F, 4/size*/, std::min(A, 4));
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	696 HighI->addMemOperand(MF, Tmp2);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	697 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	698 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	699
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	700 void HexagonSplitDoubleRegs::splitImmediate(MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	701 const UUPairMap &PairMap) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	702 MachineOperand &Op0 = MI->getOperand(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	703 MachineOperand &Op1 = MI->getOperand(1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	704 assert(Op0.isReg() && Op1.isImm());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	705 uint64_t V = Op1.getImm();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	706
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	707 MachineBasicBlock &B = *MI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	708 DebugLoc DL = MI->getDebugLoc();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	709 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	710 assert(F != PairMap.end());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	711 const UUPair &P = F->second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	712
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	713 // The operand to A2_tfrsi can only have 32 significant bits. Immediate
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	714 // values in MachineOperand are stored as 64-bit integers, and so the
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	715 // value -1 may be represented either as 64-bit -1, or 4294967295. Both
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	716 // will have the 32 higher bits truncated in the end, but -1 will remain
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	717 // as -1, while the latter may appear to be a large unsigned value
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	718 // requiring a constant extender. The casting to int32_t will select the
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	719 // former representation. (The same reasoning applies to all 32-bit
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	720 // values.)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	721 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	722 .addImm(int32_t(V & 0xFFFFFFFFULL));
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	723 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	724 .addImm(int32_t(V >> 32));
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	725 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	726
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	727 void HexagonSplitDoubleRegs::splitCombine(MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	728 const UUPairMap &PairMap) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	729 MachineOperand &Op0 = MI->getOperand(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	730 MachineOperand &Op1 = MI->getOperand(1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	731 MachineOperand &Op2 = MI->getOperand(2);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	732 assert(Op0.isReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	733
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	734 MachineBasicBlock &B = *MI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	735 DebugLoc DL = MI->getDebugLoc();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	736 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	737 assert(F != PairMap.end());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	738 const UUPair &P = F->second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	739
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	740 if (!Op1.isReg()) {
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	741 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	742 .add(Op1);
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	743 } else {
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	744 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	745 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	746 }
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	747
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	748 if (!Op2.isReg()) {
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	749 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	750 .add(Op2);
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	751 } else {
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	752 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	753 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	754 }
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	755 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	756
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	757 void HexagonSplitDoubleRegs::splitExt(MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	758 const UUPairMap &PairMap) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	759 MachineOperand &Op0 = MI->getOperand(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	760 MachineOperand &Op1 = MI->getOperand(1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	761 assert(Op0.isReg() && Op1.isReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	762
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	763 MachineBasicBlock &B = *MI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	764 DebugLoc DL = MI->getDebugLoc();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	765 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	766 assert(F != PairMap.end());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	767 const UUPair &P = F->second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	768 unsigned RS = getRegState(Op1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	769
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	770 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	771 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	772 BuildMI(B, MI, DL, TII->get(Hexagon::S2_asr_i_r), P.second)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	773 .addReg(Op1.getReg(), RS, Op1.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	774 .addImm(31);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	775 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	776
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	777 void HexagonSplitDoubleRegs::splitShift(MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	778 const UUPairMap &PairMap) {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	779 using namespace Hexagon;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	780
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	781 MachineOperand &Op0 = MI->getOperand(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	782 MachineOperand &Op1 = MI->getOperand(1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	783 MachineOperand &Op2 = MI->getOperand(2);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	784 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	785 int64_t Sh64 = Op2.getImm();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	786 assert(Sh64 >= 0 && Sh64 < 64);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	787 unsigned S = Sh64;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	788
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	789 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	790 assert(F != PairMap.end());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	791 const UUPair &P = F->second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	792 unsigned LoR = P.first;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	793 unsigned HiR = P.second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	794
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	795 unsigned Opc = MI->getOpcode();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	796 bool Right = (Opc == S2_lsr_i_p \|\| Opc == S2_asr_i_p);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	797 bool Left = !Right;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	798 bool Signed = (Opc == S2_asr_i_p);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	799
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	800 MachineBasicBlock &B = *MI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	801 DebugLoc DL = MI->getDebugLoc();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	802 unsigned RS = getRegState(Op1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	803 unsigned ShiftOpc = Left ? S2_asl_i_r
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	804 : (Signed ? S2_asr_i_r : S2_lsr_i_r);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	805 unsigned LoSR = isub_lo;
1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	806 unsigned HiSR = isub_hi;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	807
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	808 if (S == 0) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	809 // No shift, subregister copy.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	810 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	811 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	812 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	813 .addReg(Op1.getReg(), RS, HiSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	814 } else if (S < 32) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	815 const TargetRegisterClass *IntRC = &IntRegsRegClass;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	816 unsigned TmpR = MRI->createVirtualRegister(IntRC);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	817 // Expansion:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	818 // Shift left: DR = shl R, #s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	819 // LoR = shl R.lo, #s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	820 // TmpR = extractu R.lo, #s, #32-s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	821 // HiR = or (TmpR, asl(R.hi, #s))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	822 // Shift right: DR = shr R, #s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	823 // HiR = shr R.hi, #s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	824 // TmpR = shr R.lo, #s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	825 // LoR = insert TmpR, R.hi, #s, #32-s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	826
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	827 // Shift left:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	828 // LoR = shl R.lo, #s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	829 // Shift right:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	830 // TmpR = shr R.lo, #s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	831
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	832 // Make a special case for A2_aslh and A2_asrh (they are predicable as
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	833 // opposed to S2_asl_i_r/S2_asr_i_r).
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	834 if (S == 16 && Left)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	835 BuildMI(B, MI, DL, TII->get(A2_aslh), LoR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	836 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	837 else if (S == 16 && Signed)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	838 BuildMI(B, MI, DL, TII->get(A2_asrh), TmpR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	839 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	840 else
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	841 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	842 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	843 .addImm(S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	844
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	845 if (Left) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	846 // TmpR = extractu R.lo, #s, #32-s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	847 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	848 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	849 .addImm(S)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	850 .addImm(32-S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	851 // HiR = or (TmpR, asl(R.hi, #s))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	852 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	853 .addReg(TmpR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	854 .addReg(Op1.getReg(), RS, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	855 .addImm(S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	856 } else {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	857 // HiR = shr R.hi, #s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	858 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	859 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	860 .addImm(S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	861 // LoR = insert TmpR, R.hi, #s, #32-s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	862 BuildMI(B, MI, DL, TII->get(S2_insert), LoR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	863 .addReg(TmpR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	864 .addReg(Op1.getReg(), RS, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	865 .addImm(S)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	866 .addImm(32-S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	867 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	868 } else if (S == 32) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	869 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), (Left ? HiR : LoR))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	870 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	871 if (!Signed)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	872 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	873 .addImm(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	874 else // Must be right shift.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	875 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	876 .addReg(Op1.getReg(), RS, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	877 .addImm(31);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	878 } else if (S < 64) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	879 S -= 32;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	880 if (S == 16 && Left)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	881 BuildMI(B, MI, DL, TII->get(A2_aslh), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	882 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	883 else if (S == 16 && Signed)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	884 BuildMI(B, MI, DL, TII->get(A2_asrh), LoR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	885 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	886 else
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	887 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	888 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	889 .addImm(S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	890
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	891 if (Signed)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	892 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	893 .addReg(Op1.getReg(), RS, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	894 .addImm(31);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	895 else
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	896 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	897 .addImm(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	898 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	899 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	900
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	901 void HexagonSplitDoubleRegs::splitAslOr(MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	902 const UUPairMap &PairMap) {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	903 using namespace Hexagon;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	904
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	905 MachineOperand &Op0 = MI->getOperand(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	906 MachineOperand &Op1 = MI->getOperand(1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	907 MachineOperand &Op2 = MI->getOperand(2);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	908 MachineOperand &Op3 = MI->getOperand(3);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	909 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	910 int64_t Sh64 = Op3.getImm();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	911 assert(Sh64 >= 0 && Sh64 < 64);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	912 unsigned S = Sh64;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	913
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	914 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	915 assert(F != PairMap.end());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	916 const UUPair &P = F->second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	917 unsigned LoR = P.first;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	918 unsigned HiR = P.second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	919
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	920 MachineBasicBlock &B = *MI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	921 DebugLoc DL = MI->getDebugLoc();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	922 unsigned RS1 = getRegState(Op1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	923 unsigned RS2 = getRegState(Op2);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	924 const TargetRegisterClass *IntRC = &IntRegsRegClass;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	925
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	926 unsigned LoSR = isub_lo;
1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	927 unsigned HiSR = isub_hi;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	928
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	929 // Op0 = S2_asl_i_p_or Op1, Op2, Op3
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	930 // means: Op0 = or (Op1, asl(Op2, Op3))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	931
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	932 // Expansion of
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	933 // DR = or (R1, asl(R2, #s))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	934 //
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	935 // LoR = or (R1.lo, asl(R2.lo, #s))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	936 // Tmp1 = extractu R2.lo, #s, #32-s
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	937 // Tmp2 = or R1.hi, Tmp1
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	938 // HiR = or (Tmp2, asl(R2.hi, #s))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	939
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	940 if (S == 0) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	941 // DR = or (R1, asl(R2, #0))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	942 // -> or (R1, R2)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	943 // i.e. LoR = or R1.lo, R2.lo
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	944 // HiR = or R1.hi, R2.hi
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	945 BuildMI(B, MI, DL, TII->get(A2_or), LoR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	946 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	947 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	948 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	949 .addReg(Op1.getReg(), RS1, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	950 .addReg(Op2.getReg(), RS2, HiSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	951 } else if (S < 32) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	952 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), LoR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	953 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	954 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	955 .addImm(S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	956 unsigned TmpR1 = MRI->createVirtualRegister(IntRC);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	957 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR1)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	958 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	959 .addImm(S)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	960 .addImm(32-S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	961 unsigned TmpR2 = MRI->createVirtualRegister(IntRC);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	962 BuildMI(B, MI, DL, TII->get(A2_or), TmpR2)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	963 .addReg(Op1.getReg(), RS1, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	964 .addReg(TmpR1);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	965 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	966 .addReg(TmpR2)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	967 .addReg(Op2.getReg(), RS2, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	968 .addImm(S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	969 } else if (S == 32) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	970 // DR = or (R1, asl(R2, #32))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	971 // -> or R1, R2.lo
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	972 // LoR = R1.lo
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	973 // HiR = or R1.hi, R2.lo
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	974 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	975 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	976 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	977 .addReg(Op1.getReg(), RS1, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	978 .addReg(Op2.getReg(), RS2, LoSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	979 } else if (S < 64) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	980 // DR = or (R1, asl(R2, #s))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	981 //
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	982 // LoR = R1:lo
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	983 // HiR = or (R1:hi, asl(R2:lo, #s-32))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	984 S -= 32;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	985 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	986 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	987 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	988 .addReg(Op1.getReg(), RS1, HiSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	989 .addReg(Op2.getReg(), RS2, LoSR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	990 .addImm(S);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	991 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	992 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	993
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	994 bool HexagonSplitDoubleRegs::splitInstr(MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	995 const UUPairMap &PairMap) {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	996 using namespace Hexagon;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	997
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	998 LLVM_DEBUG(dbgs() << "Splitting: " << *MI);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	999 bool Split = false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1000 unsigned Opc = MI->getOpcode();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1001
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1002 switch (Opc) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1003 case TargetOpcode::PHI:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1004 case TargetOpcode::COPY: {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1005 unsigned DstR = MI->getOperand(0).getReg();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1006 if (MRI->getRegClass(DstR) == DoubleRC) {
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1007 createHalfInstr(Opc, MI, PairMap, isub_lo);
1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1008 createHalfInstr(Opc, MI, PairMap, isub_hi);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1009 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1010 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1011 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1012 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1013 case A2_andp:
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1014 createHalfInstr(A2_and, MI, PairMap, isub_lo);
1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1015 createHalfInstr(A2_and, MI, PairMap, isub_hi);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1016 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1017 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1018 case A2_orp:
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1019 createHalfInstr(A2_or, MI, PairMap, isub_lo);
1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1020 createHalfInstr(A2_or, MI, PairMap, isub_hi);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1021 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1022 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1023 case A2_xorp:
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1024 createHalfInstr(A2_xor, MI, PairMap, isub_lo);
1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1025 createHalfInstr(A2_xor, MI, PairMap, isub_hi);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1026 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1027 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1028
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1029 case L2_loadrd_io:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1030 case L2_loadrd_pi:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1031 case S2_storerd_io:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1032 case S2_storerd_pi:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1033 splitMemRef(MI, PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1034 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1035 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1036
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1037 case A2_tfrpi:
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1038 case CONST64:
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1039 splitImmediate(MI, PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1040 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1041 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1042
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1043 case A2_combineii:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1044 case A4_combineir:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1045 case A4_combineii:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1046 case A4_combineri:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1047 case A2_combinew:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1048 splitCombine(MI, PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1049 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1050 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1051
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1052 case A2_sxtw:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1053 splitExt(MI, PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1054 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1055 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1056
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1057 case S2_asl_i_p:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1058 case S2_asr_i_p:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1059 case S2_lsr_i_p:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1060 splitShift(MI, PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1061 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1062 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1063
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1064 case S2_asl_i_p_or:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1065 splitAslOr(MI, PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1066 Split = true;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1067 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1068
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1069 default:
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1070 llvm_unreachable("Instruction not splitable");
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1071 return false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1072 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1073
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1074 return Split;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1075 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1076
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1077 void HexagonSplitDoubleRegs::replaceSubregUses(MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1078 const UUPairMap &PairMap) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1079 for (auto &Op : MI->operands()) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1080 if (!Op.isReg() \|\| !Op.isUse() \|\| !Op.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1081 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1082 unsigned R = Op.getReg();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1083 UUPairMap::const_iterator F = PairMap.find(R);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1084 if (F == PairMap.end())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1085 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1086 const UUPair &P = F->second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1087 switch (Op.getSubReg()) {
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1088 case Hexagon::isub_lo:
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1089 Op.setReg(P.first);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1090 break;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1091 case Hexagon::isub_hi:
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1092 Op.setReg(P.second);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1093 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1094 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1095 Op.setSubReg(0);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1096 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1097 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1098
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1099 void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1100 const UUPairMap &PairMap) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1101 MachineBasicBlock &B = *MI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1102 DebugLoc DL = MI->getDebugLoc();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1103
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1104 for (auto &Op : MI->operands()) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1105 if (!Op.isReg() \|\| !Op.isUse())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1106 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1107 unsigned R = Op.getReg();
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1108 if (!Register::isVirtualRegister(R))
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1109 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1110 if (MRI->getRegClass(R) != DoubleRC \|\| Op.getSubReg())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1111 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1112 UUPairMap::const_iterator F = PairMap.find(R);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1113 if (F == PairMap.end())
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1114 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1115 const UUPair &Pr = F->second;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1116 unsigned NewDR = MRI->createVirtualRegister(DoubleRC);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1117 BuildMI(B, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), NewDR)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1118 .addReg(Pr.first)
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1119 .addImm(Hexagon::isub_lo)
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1120 .addReg(Pr.second)
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1121 .addImm(Hexagon::isub_hi);
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1122 Op.setReg(NewDR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1123 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1124 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1125
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	1126 bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	1127 using MISet = std::set<MachineInstr *>;
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1128
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1129 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1130 bool Changed = false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1131
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1132 LLVM_DEBUG(dbgs() << "Splitting partition: ";
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1133 dump_partition(dbgs(), Part, *TRI); dbgs() << '\n');
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1134
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1135 UUPairMap PairMap;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1136
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1137 MISet SplitIns;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1138 for (unsigned DR : Part) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1139 MachineInstr *DefI = MRI->getVRegDef(DR);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1140 SplitIns.insert(DefI);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1141
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1142 // Collect all instructions, including fixed ones. We won't split them,
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1143 // but we need to visit them again to insert the REG_SEQUENCE instructions.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1144 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1145 U != W; ++U)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1146 SplitIns.insert(U->getParent());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1147
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1148 unsigned LoR = MRI->createVirtualRegister(IntRC);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1149 unsigned HiR = MRI->createVirtualRegister(IntRC);
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1150 LLVM_DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> "
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1151 << printReg(HiR, TRI) << ':' << printReg(LoR, TRI)
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1152 << '\n');
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1153 PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR)));
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1154 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1155
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1156 MISet Erase;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1157 for (auto MI : SplitIns) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1158 if (isFixedInstr(MI)) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1159 collapseRegPairs(MI, PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1160 } else {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1161 bool Done = splitInstr(MI, PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1162 if (Done)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1163 Erase.insert(MI);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1164 Changed \|= Done;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1165 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1166 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1167
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1168 for (unsigned DR : Part) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1169 // Before erasing "double" instructions, revisit all uses of the double
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1170 // registers in this partition, and replace all uses of them with subre-
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1171 // gisters, with the corresponding single registers.
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1172 MISet Uses;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1173 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1174 U != W; ++U)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1175 Uses.insert(U->getParent());
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1176 for (auto M : Uses)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1177 replaceSubregUses(M, PairMap);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1178 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1179
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1180 for (auto MI : Erase) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1181 MachineBasicBlock *B = MI->getParent();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1182 B->erase(MI);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1183 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1184
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1185 return Changed;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1186 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1187
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1188 bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) {
134 3a76565eade5 update 5.0.1 mir3636 parents: 121 diff changeset	1189 if (skipFunction(MF.getFunction()))
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1190 return false;
1172e4bd9c6f update 4.0.0 mir3636 parents: 100 diff changeset	1191
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1192 LLVM_DEBUG(dbgs() << "Splitting double registers in function: "
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1193 << MF.getName() << '\n');
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1194
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1195 auto &ST = MF.getSubtarget<HexagonSubtarget>();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1196 TRI = ST.getRegisterInfo();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1197 TII = ST.getInstrInfo();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1198 MRI = &MF.getRegInfo();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1199 MLI = &getAnalysis<MachineLoopInfo>();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1200
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1201 UUSetMap P2Rs;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1202 LoopRegMap IRM;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1203
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1204 collectIndRegs(IRM);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1205 partitionRegisters(P2Rs);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1206
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1207 LLVM_DEBUG({
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1208 dbgs() << "Register partitioning: (partition #0 is fixed)\n";
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1209 for (UUSetMap::iterator I = P2Rs.begin(), E = P2Rs.end(); I != E; ++I) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1210 dbgs() << '#' << I->first << " -> ";
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1211 dump_partition(dbgs(), I->second, *TRI);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1212 dbgs() << '\n';
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1213 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1214 });
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1215
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1216 bool Changed = false;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1217 int Limit = MaxHSDR;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1218
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1219 for (UUSetMap::iterator I = P2Rs.begin(), E = P2Rs.end(); I != E; ++I) {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1220 if (I->first == 0)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1221 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1222 if (Limit >= 0 && Counter >= Limit)
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1223 break;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1224 USet &Part = I->second;
147 c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1225 LLVM_DEBUG(dbgs() << "Calculating profit for partition #" << I->first
c2174574ed3a LLVM 10 Shinji KONO <kono@ie.u-ryukyu.ac.jp> parents: 134 diff changeset	1226 << '\n');
100 7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1227 if (!isProfitable(Part, IRM))
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1228 continue;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1229 Counter++;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1230 Changed \|= splitPartition(Part);
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1231 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1232
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1233 return Changed;
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1234 }
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1235
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1236 FunctionPass *llvm::createHexagonSplitDoubleRegs() {
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1237 return new HexagonSplitDoubleRegs();
7d135dc70f03 LLVM 3.9 Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp> parents: diff changeset	1238 }

Mercurial > hg > CbC > CbC_llvm

annotate lib/Target/Hexagon/HexagonSplitDouble.cpp @ 147:c2174574ed3a