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121
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1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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2 ; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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120
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3
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4 ; GCN-LABEL: {{^}}fadd_f16
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121
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5 ; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
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6 ; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
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120
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7 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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8 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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121
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9 ; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
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120
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10 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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121
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11 ; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]]
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120
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12 ; GCN: buffer_store_short v[[R_F16]]
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13 ; GCN: s_endpgm
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121
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14 define amdgpu_kernel void @fadd_f16(
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120
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15 half addrspace(1)* %r,
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16 half addrspace(1)* %a,
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17 half addrspace(1)* %b) {
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18 entry:
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147
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19 %a.val = load volatile half, half addrspace(1)* %a
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20 %b.val = load volatile half, half addrspace(1)* %b
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120
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21 %r.val = fadd half %a.val, %b.val
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22 store half %r.val, half addrspace(1)* %r
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23 ret void
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24 }
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25
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26 ; GCN-LABEL: {{^}}fadd_f16_imm_a
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121
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27 ; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
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120
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28 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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121
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29 ; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], 1.0, v[[B_F32]]
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120
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30 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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121
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31 ; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 1.0, v[[B_F16]]
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120
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32 ; GCN: buffer_store_short v[[R_F16]]
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33 ; GCN: s_endpgm
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121
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34 define amdgpu_kernel void @fadd_f16_imm_a(
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120
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35 half addrspace(1)* %r,
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36 half addrspace(1)* %b) {
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37 entry:
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38 %b.val = load half, half addrspace(1)* %b
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39 %r.val = fadd half 1.0, %b.val
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40 store half %r.val, half addrspace(1)* %r
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41 ret void
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42 }
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43
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44 ; GCN-LABEL: {{^}}fadd_f16_imm_b
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121
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45 ; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
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120
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46 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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121
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47 ; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], 2.0, v[[A_F32]]
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120
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48 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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121
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49 ; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 2.0, v[[A_F16]]
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120
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50 ; GCN: buffer_store_short v[[R_F16]]
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51 ; GCN: s_endpgm
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121
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52 define amdgpu_kernel void @fadd_f16_imm_b(
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120
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53 half addrspace(1)* %r,
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54 half addrspace(1)* %a) {
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55 entry:
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56 %a.val = load half, half addrspace(1)* %a
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57 %r.val = fadd half %a.val, 2.0
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58 store half %r.val, half addrspace(1)* %r
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59 ret void
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60 }
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61
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121
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62 ; GCN-LABEL: {{^}}fadd_v2f16:
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63 ; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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64 ; SI: buffer_load_dword v[[B_V2_F16:[0-9]+]]
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65 ; VI: flat_load_dword v[[B_V2_F16:[0-9]+]]
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66 ; VI: flat_load_dword v[[A_V2_F16:[0-9]+]]
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67
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147
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68 ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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69 ; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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70 ; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]
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71 ; SI-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
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121
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72
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73 ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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74 ; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]
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75 ; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]], v[[B_F32_0]]
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76 ; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]], v[[B_F32_1]]
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77 ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
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78 ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
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79 ; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
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80 ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
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81
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82 ; VI-DAG: v_add_f16_e32 v[[R_F16_LO:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]]
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83 ; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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84 ; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_LO]], v[[R_F16_HI]]
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85
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120
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86 ; GCN: buffer_store_dword v[[R_V2_F16]]
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87 ; GCN: s_endpgm
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121
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88 define amdgpu_kernel void @fadd_v2f16(
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120
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89 <2 x half> addrspace(1)* %r,
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90 <2 x half> addrspace(1)* %a,
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91 <2 x half> addrspace(1)* %b) {
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92 entry:
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121
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93 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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94 %gep.a = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %a, i32 %tid
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95 %gep.b = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %b, i32 %tid
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96 %a.val = load <2 x half>, <2 x half> addrspace(1)* %gep.a
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97 %b.val = load <2 x half>, <2 x half> addrspace(1)* %gep.b
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120
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98 %r.val = fadd <2 x half> %a.val, %b.val
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99 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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100 ret void
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101 }
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102
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121
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103 ; GCN-LABEL: {{^}}fadd_v2f16_imm_a:
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104 ; GCN-DAG: {{buffer|flat}}_load_dword v[[B_V2_F16:[0-9]+]]
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147
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105 ; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]
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106 ; SI-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
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107 ; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]
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108 ; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 1.0, v[[B_F32_0]]
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109 ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
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110 ; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], 2.0, v[[B_F32_1]]
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111 ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
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121
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112 ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
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113 ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
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114
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115 ; VI-DAG: v_mov_b32_e32 v[[CONST2:[0-9]+]], 0x4000
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116 ; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[B_V2_F16]], v[[CONST2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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117 ; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], 1.0, v[[B_V2_F16]]
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118 ; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
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119
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120
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120 ; GCN: buffer_store_dword v[[R_V2_F16]]
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121 ; GCN: s_endpgm
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121
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122 define amdgpu_kernel void @fadd_v2f16_imm_a(
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120
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123 <2 x half> addrspace(1)* %r,
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124 <2 x half> addrspace(1)* %b) {
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125 entry:
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121
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126 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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127 %gep.b = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %b, i32 %tid
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128 %b.val = load <2 x half>, <2 x half> addrspace(1)* %gep.b
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120
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129 %r.val = fadd <2 x half> <half 1.0, half 2.0>, %b.val
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130 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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131 ret void
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132 }
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133
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121
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134 ; GCN-LABEL: {{^}}fadd_v2f16_imm_b:
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135 ; GCN-DAG: {{buffer|flat}}_load_dword v[[A_V2_F16:[0-9]+]]
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147
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136 ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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121
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137 ; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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147
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138 ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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139 ; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 2.0, v[[A_F32_0]]
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140 ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
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141 ; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], 1.0, v[[A_F32_1]]
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142 ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
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121
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143 ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
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144 ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
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145
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146 ; VI-DAG: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00
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147 ; VI-DAG: v_add_f16_sdwa v[[R_F16_0:[0-9]+]], v[[A_V2_F16]], v[[CONST1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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148 ; VI-DAG: v_add_f16_e32 v[[R_F16_1:[0-9]+]], 2.0, v[[A_V2_F16]]
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149 ; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
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150
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120
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151 ; GCN: buffer_store_dword v[[R_V2_F16]]
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152 ; GCN: s_endpgm
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121
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153 define amdgpu_kernel void @fadd_v2f16_imm_b(
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120
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154 <2 x half> addrspace(1)* %r,
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155 <2 x half> addrspace(1)* %a) {
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156 entry:
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121
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157 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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158 %gep.a = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %a, i32 %tid
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159 %a.val = load <2 x half>, <2 x half> addrspace(1)* %gep.a
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120
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160 %r.val = fadd <2 x half> %a.val, <half 2.0, half 1.0>
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161 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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162 ret void
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163 }
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121
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164
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165 declare i32 @llvm.amdgcn.workitem.id.x() #1
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166
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167 attributes #0 = { nounwind }
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168 attributes #1 = { nounwind readnone }
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