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annotate test/Transforms/InstCombine/align-addr.ll @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 3a76565eade5
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
147
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1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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2 ; RUN: opt < %s -instcombine -S | FileCheck %s
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3 target datalayout = "E-p:64:64:64-p1:32:32:32-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
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4
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5 ; Instcombine should be able to prove vector alignment in the
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6 ; presence of a few mild address computation tricks.
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7
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8 define void @test0(i8* %b, i64 %n, i64 %u, i64 %y) nounwind {
0
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9 ; CHECK-LABEL: @test0(
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10 ; CHECK-NEXT: entry:
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11 ; CHECK-NEXT: [[C:%.*]] = ptrtoint i8* [[B:%.*]] to i64
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12 ; CHECK-NEXT: [[D:%.*]] = and i64 [[C]], -16
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13 ; CHECK-NEXT: [[E:%.*]] = inttoptr i64 [[D]] to double*
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14 ; CHECK-NEXT: [[V:%.*]] = shl i64 [[U:%.*]], 1
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15 ; CHECK-NEXT: [[Z:%.*]] = and i64 [[Y:%.*]], -2
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16 ; CHECK-NEXT: [[T1421:%.*]] = icmp eq i64 [[N:%.*]], 0
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17 ; CHECK-NEXT: br i1 [[T1421]], label [[RETURN:%.*]], label [[BB:%.*]]
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18 ; CHECK: bb:
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19 ; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[BB]] ], [ 20, [[ENTRY:%.*]] ]
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20 ; CHECK-NEXT: [[J:%.*]] = mul i64 [[I]], [[V]]
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21 ; CHECK-NEXT: [[H:%.*]] = add i64 [[J]], [[Z]]
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22 ; CHECK-NEXT: [[T8:%.*]] = getelementptr double, double* [[E]], i64 [[H]]
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23 ; CHECK-NEXT: [[P:%.*]] = bitcast double* [[T8]] to <2 x double>*
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24 ; CHECK-NEXT: store <2 x double> zeroinitializer, <2 x double>* [[P]], align 16
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25 ; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[I]], 1
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26 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVAR_NEXT]], [[N]]
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27 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[RETURN]], label [[BB]]
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28 ; CHECK: return:
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29 ; CHECK-NEXT: ret void
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30 ;
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31 entry:
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32 %c = ptrtoint i8* %b to i64
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33 %d = and i64 %c, -16
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34 %e = inttoptr i64 %d to double*
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35 %v = mul i64 %u, 2
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36 %z = and i64 %y, -2
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37 %t1421 = icmp eq i64 %n, 0
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38 br i1 %t1421, label %return, label %bb
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39
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40 bb:
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41 %i = phi i64 [ %indvar.next, %bb ], [ 20, %entry ]
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42 %j = mul i64 %i, %v
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43 %h = add i64 %j, %z
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44 %t8 = getelementptr double, double* %e, i64 %h
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45 %p = bitcast double* %t8 to <2 x double>*
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46 store <2 x double><double 0.0, double 0.0>, <2 x double>* %p, align 8
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47 %indvar.next = add i64 %i, 1
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48 %exitcond = icmp eq i64 %indvar.next, %n
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49 br i1 %exitcond, label %return, label %bb
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50
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51 return:
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52 ret void
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53 }
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54
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55 ; When we see a unaligned load from an insufficiently aligned global or
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56 ; alloca, increase the alignment of the load, turning it into an aligned load.
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57
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58 @GLOBAL = internal global [4 x i32] zeroinitializer
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59
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60 define <16 x i8> @test1(<2 x i64> %x) {
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61 ; CHECK-LABEL: @test1(
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62 ; CHECK-NEXT: entry:
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63 ; CHECK-NEXT: [[TMP:%.*]] = load <16 x i8>, <16 x i8>* bitcast ([4 x i32]* @GLOBAL to <16 x i8>*), align 16
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64 ; CHECK-NEXT: ret <16 x i8> [[TMP]]
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65 ;
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66 entry:
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67 %tmp = load <16 x i8>, <16 x i8>* bitcast ([4 x i32]* @GLOBAL to <16 x i8>*), align 1
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68 ret <16 x i8> %tmp
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69 }
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70
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71 @GLOBAL_as1 = internal addrspace(1) global [4 x i32] zeroinitializer
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72
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73 define <16 x i8> @test1_as1(<2 x i64> %x) {
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74 ; CHECK-LABEL: @test1_as1(
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75 ; CHECK-NEXT: [[TMP:%.*]] = load <16 x i8>, <16 x i8> addrspace(1)* bitcast ([4 x i32] addrspace(1)* @GLOBAL_as1 to <16 x i8> addrspace(1)*), align 16
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76 ; CHECK-NEXT: ret <16 x i8> [[TMP]]
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77 ;
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78 %tmp = load <16 x i8>, <16 x i8> addrspace(1)* bitcast ([4 x i32] addrspace(1)* @GLOBAL_as1 to <16 x i8> addrspace(1)*), align 1
0
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79 ret <16 x i8> %tmp
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80 }
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81
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82 @GLOBAL_as1_gep = internal addrspace(1) global [8 x i32] zeroinitializer
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83
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84 define <16 x i8> @test1_as1_gep(<2 x i64> %x) {
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85 ; CHECK-LABEL: @test1_as1_gep(
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86 ; CHECK-NEXT: [[TMP:%.*]] = load <16 x i8>, <16 x i8> addrspace(1)* bitcast (i32 addrspace(1)* getelementptr inbounds ([8 x i32], [8 x i32] addrspace(1)* @GLOBAL_as1_gep, i32 0, i32 4) to <16 x i8> addrspace(1)*), align 16
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87 ; CHECK-NEXT: ret <16 x i8> [[TMP]]
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88 ;
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89 %tmp = load <16 x i8>, <16 x i8> addrspace(1)* bitcast (i32 addrspace(1)* getelementptr ([8 x i32], [8 x i32] addrspace(1)* @GLOBAL_as1_gep, i16 0, i16 4) to <16 x i8> addrspace(1)*), align 1
0
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90 ret <16 x i8> %tmp
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91 }
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92
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93
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94 ; When a load or store lacks an explicit alignment, add one.
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95
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96 define double @test2(double* %p, double %n) nounwind {
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97 ; CHECK-LABEL: @test2(
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98 ; CHECK-NEXT: [[T:%.*]] = load double, double* [[P:%.*]], align 8
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99 ; CHECK-NEXT: store double [[N:%.*]], double* [[P]], align 8
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100 ; CHECK-NEXT: ret double [[T]]
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101 ;
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102 %t = load double, double* %p
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103 store double %n, double* %p
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104 ret double %t
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105 }
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106
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107 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
0
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108
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109 declare void @use(i8*)
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110
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111 %struct.s = type { i32, i32, i32, i32 }
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112
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113 define void @test3(%struct.s* sret %a4) {
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114 ; Check that the alignment is bumped up the alignment of the sret type.
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115 ; CHECK-LABEL: @test3(
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116 ; CHECK-NEXT: [[A4_CAST:%.*]] = bitcast %struct.s* [[A4:%.*]] to i8*
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117 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 4 dereferenceable(16) [[A4_CAST]], i8 0, i64 16, i1 false)
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118 ; CHECK-NEXT: call void @use(i8* [[A4_CAST]])
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Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 134
diff changeset
119 ; CHECK-NEXT: ret void
c2174574ed3a LLVM 10
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 134
diff changeset
120 ;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
121 %a4.cast = bitcast %struct.s* %a4 to i8*
134
3a76565eade5 update 5.0.1
mir3636
parents: 95
diff changeset
122 call void @llvm.memset.p0i8.i64(i8* %a4.cast, i8 0, i64 16, i1 false)
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
123 call void @use(i8* %a4.cast)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
124 ret void
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
125 }