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120
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1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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2 ; RUN: opt < %s -instcombine -S | FileCheck %s
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 define i1 @test2(i1 %X, i1 %Y) {
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120
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5 ; CHECK-LABEL: @test2(
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6 ; CHECK-NEXT: [[B:%.*]] = and i1 %X, %Y
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7 ; CHECK-NEXT: ret i1 [[B]]
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8 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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9 %a = and i1 %X, %Y
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 %b = and i1 %a, %X
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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11 ret i1 %b
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14 define i32 @test3(i32 %X, i32 %Y) {
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120
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15 ; CHECK-LABEL: @test3(
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16 ; CHECK-NEXT: [[B:%.*]] = and i32 %X, %Y
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17 ; CHECK-NEXT: ret i32 [[B]]
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18 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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19 %a = and i32 %X, %Y
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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20 %b = and i32 %Y, %a
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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21 ret i32 %b
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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22 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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23
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77
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24 define i1 @test7(i32 %i, i1 %b) {
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25 ; CHECK-LABEL: @test7(
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120
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26 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %i, 0
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27 ; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[TMP1]], %b
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28 ; CHECK-NEXT: ret i1 [[TMP2]]
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29 ;
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77
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30 %cmp1 = icmp slt i32 %i, 1
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31 %cmp2 = icmp sgt i32 %i, -1
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32 %and1 = and i1 %cmp1, %b
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33 %and2 = and i1 %and1, %cmp2
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34 ret i1 %and2
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35 }
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83
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36
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37 define i1 @test8(i32 %i) {
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38 ; CHECK-LABEL: @test8(
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120
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39 ; CHECK-NEXT: [[I_OFF:%.*]] = add i32 %i, -1
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40 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[I_OFF]], 13
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41 ; CHECK-NEXT: ret i1 [[TMP1]]
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42 ;
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83
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43 %cmp1 = icmp ne i32 %i, 0
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44 %cmp2 = icmp ult i32 %i, 14
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45 %cond = and i1 %cmp1, %cmp2
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46 ret i1 %cond
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47 }
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95
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48
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120
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49 ; FIXME: Vectors should fold too.
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50 define <2 x i1> @test8vec(<2 x i32> %i) {
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51 ; CHECK-LABEL: @test8vec(
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52 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne <2 x i32> %i, zeroinitializer
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53 ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult <2 x i32> %i, <i32 14, i32 14>
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54 ; CHECK-NEXT: [[COND:%.*]] = and <2 x i1> [[CMP1]], [[CMP2]]
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55 ; CHECK-NEXT: ret <2 x i1> [[COND]]
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56 ;
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57 %cmp1 = icmp ne <2 x i32> %i, zeroinitializer
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58 %cmp2 = icmp ult <2 x i32> %i, <i32 14, i32 14>
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59 %cond = and <2 x i1> %cmp1, %cmp2
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60 ret <2 x i1> %cond
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61 }
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62
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95
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63 ; combine -x & 1 into x & 1
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64 define i64 @test9(i64 %x) {
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65 ; CHECK-LABEL: @test9(
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120
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66 ; CHECK-NEXT: [[AND:%.*]] = and i64 %x, 1
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67 ; CHECK-NEXT: ret i64 [[AND]]
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68 ;
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95
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69 %sub = sub nsw i64 0, %x
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70 %and = and i64 %sub, 1
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71 ret i64 %and
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72 }
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73
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121
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74 ; combine -x & 1 into x & 1
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75 define <2 x i64> @test9vec(<2 x i64> %x) {
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76 ; CHECK-LABEL: @test9vec(
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77 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> %x, <i64 1, i64 1>
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78 ; CHECK-NEXT: ret <2 x i64> [[AND]]
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79 ;
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80 %sub = sub nsw <2 x i64> <i64 0, i64 0>, %x
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81 %and = and <2 x i64> %sub, <i64 1, i64 1>
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82 ret <2 x i64> %and
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83 }
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84
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95
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85 define i64 @test10(i64 %x) {
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86 ; CHECK-LABEL: @test10(
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120
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87 ; CHECK-NEXT: [[AND:%.*]] = and i64 %x, 1
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88 ; CHECK-NEXT: [[ADD:%.*]] = sub i64 [[AND]], %x
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89 ; CHECK-NEXT: ret i64 [[ADD]]
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90 ;
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95
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91 %sub = sub nsw i64 0, %x
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92 %and = and i64 %sub, 1
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93 %add = add i64 %sub, %and
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94 ret i64 %add
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95 }
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96
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121
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97 ; (1 << x) & 1 --> zext(x == 0)
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98
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99 define i8 @and1_shl1_is_cmp_eq_0(i8 %x) {
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100 ; CHECK-LABEL: @and1_shl1_is_cmp_eq_0(
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101 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 %x, 0
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102 ; CHECK-NEXT: [[AND:%.*]] = zext i1 [[TMP1]] to i8
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103 ; CHECK-NEXT: ret i8 [[AND]]
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104 ;
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105 %sh = shl i8 1, %x
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106 %and = and i8 %sh, 1
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107 ret i8 %and
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108 }
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109
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110 ; Don't do it if the shift has another use.
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111
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112 define i8 @and1_shl1_is_cmp_eq_0_multiuse(i8 %x) {
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113 ; CHECK-LABEL: @and1_shl1_is_cmp_eq_0_multiuse(
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114 ; CHECK-NEXT: [[SH:%.*]] = shl i8 1, %x
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115 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[SH]], 1
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116 ; CHECK-NEXT: [[ADD:%.*]] = add i8 [[SH]], [[AND]]
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117 ; CHECK-NEXT: ret i8 [[ADD]]
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118 ;
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119 %sh = shl i8 1, %x
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120 %and = and i8 %sh, 1
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121 %add = add i8 %sh, %and
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122 ret i8 %add
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123 }
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124
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125 ; (1 << x) & 1 --> zext(x == 0)
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126
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127 define <2 x i8> @and1_shl1_is_cmp_eq_0_vec(<2 x i8> %x) {
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128 ; CHECK-LABEL: @and1_shl1_is_cmp_eq_0_vec(
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129 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> %x, zeroinitializer
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130 ; CHECK-NEXT: [[AND:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
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131 ; CHECK-NEXT: ret <2 x i8> [[AND]]
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132 ;
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133 %sh = shl <2 x i8> <i8 1, i8 1>, %x
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134 %and = and <2 x i8> %sh, <i8 1, i8 1>
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135 ret <2 x i8> %and
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136 }
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137
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138 ; (1 >> x) & 1 --> zext(x == 0)
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139
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140 define i8 @and1_lshr1_is_cmp_eq_0(i8 %x) {
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141 ; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0(
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142 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 %x, 0
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143 ; CHECK-NEXT: [[AND:%.*]] = zext i1 [[TMP1]] to i8
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144 ; CHECK-NEXT: ret i8 [[AND]]
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145 ;
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146 %sh = lshr i8 1, %x
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147 %and = and i8 %sh, 1
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148 ret i8 %and
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149 }
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150
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151 ; Don't do it if the shift has another use.
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152
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153 define i8 @and1_lshr1_is_cmp_eq_0_multiuse(i8 %x) {
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154 ; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_multiuse(
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155 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 1, %x
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156 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[SH]], 1
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147
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157 ; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i8 [[SH]], [[AND]]
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121
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158 ; CHECK-NEXT: ret i8 [[ADD]]
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159 ;
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160 %sh = lshr i8 1, %x
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161 %and = and i8 %sh, 1
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162 %add = add i8 %sh, %and
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163 ret i8 %add
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164 }
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165
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166 ; (1 >> x) & 1 --> zext(x == 0)
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167
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168 define <2 x i8> @and1_lshr1_is_cmp_eq_0_vec(<2 x i8> %x) {
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169 ; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_vec(
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170 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> %x, zeroinitializer
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171 ; CHECK-NEXT: [[AND:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
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172 ; CHECK-NEXT: ret <2 x i8> [[AND]]
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173 ;
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174 %sh = lshr <2 x i8> <i8 1, i8 1>, %x
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175 %and = and <2 x i8> %sh, <i8 1, i8 1>
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176 ret <2 x i8> %and
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177 }
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178
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179 ; The add in this test is unnecessary because the LSBs of the LHS are 0 and the 'and' only consumes bits from those LSBs. It doesn't matter what happens to the upper bits.
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180 define i32 @test11(i32 %a, i32 %b) {
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181 ; CHECK-LABEL: @test11(
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182 ; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8
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183 ; CHECK-NEXT: [[Z:%.*]] = and i32 [[B:%.*]], 128
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184 ; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]]
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185 ; CHECK-NEXT: ret i32 [[W]]
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186 ;
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187 %x = shl i32 %a, 8
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188 %y = add i32 %x, %b
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189 %z = and i32 %y, 128
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190 %w = mul i32 %z, %x ; to keep the shift from being removed
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191 ret i32 %w
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192 }
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193
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194 ; The add in this test is unnecessary because the LSBs of the RHS are 0 and the 'and' only consumes bits from those LSBs. It doesn't matter what happens to the upper bits.
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195 define i32 @test12(i32 %a, i32 %b) {
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196 ; CHECK-LABEL: @test12(
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197 ; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8
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198 ; CHECK-NEXT: [[Z:%.*]] = and i32 [[B:%.*]], 128
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199 ; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]]
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200 ; CHECK-NEXT: ret i32 [[W]]
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201 ;
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202 %x = shl i32 %a, 8
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203 %y = add i32 %b, %x
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204 %z = and i32 %y, 128
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205 %w = mul i32 %z, %x ; to keep the shift from being removed
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206 ret i32 %w
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207 }
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208
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209 ; The sub in this test is unnecessary because the LSBs of the RHS are 0 and the 'and' only consumes bits from those LSBs. It doesn't matter what happens to the upper bits.
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210 define i32 @test13(i32 %a, i32 %b) {
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211 ; CHECK-LABEL: @test13(
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212 ; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8
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213 ; CHECK-NEXT: [[Z:%.*]] = and i32 [[B:%.*]], 128
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214 ; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]]
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215 ; CHECK-NEXT: ret i32 [[W]]
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216 ;
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217 %x = shl i32 %a, 8
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218 %y = sub i32 %b, %x
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219 %z = and i32 %y, 128
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220 %w = mul i32 %z, %x ; to keep the shift from being removed
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221 ret i32 %w
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222 }
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223
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224 ; The sub in this test cannot be removed because we need to keep the negation of %b. TODO: But we should be able to replace the LHS of it with a 0.
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225 define i32 @test14(i32 %a, i32 %b) {
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226 ; CHECK-LABEL: @test14(
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227 ; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8
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228 ; CHECK-NEXT: [[Y:%.*]] = sub i32 0, [[B:%.*]]
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229 ; CHECK-NEXT: [[Z:%.*]] = and i32 [[Y]], 128
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230 ; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]]
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231 ; CHECK-NEXT: ret i32 [[W]]
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232 ;
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233 %x = shl i32 %a, 8
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234 %y = sub i32 %x, %b
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235 %z = and i32 %y, 128
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236 %w = mul i32 %z, %x ; to keep the shift from being removed
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237 ret i32 %w
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238 }
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