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147
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1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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2 ; RUN: opt %s -instcombine -S | FileCheck %s
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3
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4 ; Given pattern:
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5 ; (trunc (x << Q) to iDst) << K
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6 ; we should rewrite it as
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7 ; (trunc (x << (Q+K)) to iDst) iff (Q+K) u< iDst
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8 ; This is only valid for shl.
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9 ; THIS FOLD DOES *NOT* REQUIRE ANY 'nuw'/`nsw` FLAGS!
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10
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11 ; Basic scalar test
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12
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13 define i16 @t0(i32 %x, i16 %y) {
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14 ; CHECK-LABEL: @t0(
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15 ; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
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16 ; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
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17 ; CHECK-NEXT: ret i16 [[T5]]
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18 ;
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19 %t0 = sub i16 32, %y
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20 %t1 = zext i16 %t0 to i32
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21 %t2 = shl i32 %x, %t1
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22 %t3 = trunc i32 %t2 to i16
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23 %t4 = add i16 %y, -24
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24 %t5 = shl i16 %t3, %t4
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25 ret i16 %t5
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26 }
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27
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28 define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) {
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29 ; CHECK-LABEL: @t1_vec_splat(
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30 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 8, i32 8>
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31 ; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
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32 ; CHECK-NEXT: ret <2 x i16> [[T5]]
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33 ;
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34 %t0 = sub <2 x i16> <i16 32, i16 32>, %y
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35 %t1 = zext <2 x i16> %t0 to <2 x i32>
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36 %t2 = shl <2 x i32> %x, %t1
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37 %t3 = trunc <2 x i32> %t2 to <2 x i16>
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38 %t4 = add <2 x i16> %y, <i16 -24, i16 -24>
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39 %t5 = shl <2 x i16> %t3, %t4
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40 ret <2 x i16> %t5
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41 }
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42
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43 define <2 x i16> @t2_vec_nonsplat(<2 x i32> %x, <2 x i16> %y) {
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44 ; CHECK-LABEL: @t2_vec_nonsplat(
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45 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 8, i32 30>
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46 ; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
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47 ; CHECK-NEXT: ret <2 x i16> [[T5]]
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48 ;
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49 %t0 = sub <2 x i16> <i16 32, i16 30>, %y
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50 %t1 = zext <2 x i16> %t0 to <2 x i32>
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51 %t2 = shl <2 x i32> %x, %t1
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52 %t3 = trunc <2 x i32> %t2 to <2 x i16>
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53 %t4 = add <2 x i16> %y, <i16 -24, i16 0>
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54 %t5 = shl <2 x i16> %t3, %t4
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55 ret <2 x i16> %t5
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56 }
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57
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58 ; Basic vector tests
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59
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60 define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
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61 ; CHECK-LABEL: @t3_vec_nonsplat_undef0(
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62 ; CHECK-NEXT: [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 8, i32 0, i32 8>
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63 ; CHECK-NEXT: [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
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64 ; CHECK-NEXT: ret <3 x i16> [[T5]]
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65 ;
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66 %t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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67 %t1 = zext <3 x i16> %t0 to <3 x i32>
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68 %t2 = shl <3 x i32> %x, %t1
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69 %t3 = trunc <3 x i32> %t2 to <3 x i16>
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70 %t4 = add <3 x i16> %y, <i16 -24, i16 -24, i16 -24>
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71 %t5 = shl <3 x i16> %t3, %t4
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72 ret <3 x i16> %t5
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73 }
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74
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75 define <3 x i16> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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76 ; CHECK-LABEL: @t4_vec_nonsplat_undef1(
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77 ; CHECK-NEXT: [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 8, i32 0, i32 8>
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78 ; CHECK-NEXT: [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
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79 ; CHECK-NEXT: ret <3 x i16> [[T5]]
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80 ;
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81 %t0 = sub <3 x i16> <i16 32, i16 32, i16 32>, %y
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82 %t1 = zext <3 x i16> %t0 to <3 x i32>
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83 %t2 = shl <3 x i32> %x, %t1
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84 %t3 = trunc <3 x i32> %t2 to <3 x i16>
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85 %t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
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86 %t5 = shl <3 x i16> %t3, %t4
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87 ret <3 x i16> %t5
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88 }
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89
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90 define <3 x i16> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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91 ; CHECK-LABEL: @t5_vec_nonsplat_undef1(
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92 ; CHECK-NEXT: [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 8, i32 0, i32 8>
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93 ; CHECK-NEXT: [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
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94 ; CHECK-NEXT: ret <3 x i16> [[T5]]
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95 ;
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96 %t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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97 %t1 = zext <3 x i16> %t0 to <3 x i32>
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98 %t2 = shl <3 x i32> %x, %t1
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99 %t3 = trunc <3 x i32> %t2 to <3 x i16>
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100 %t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
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101 %t5 = shl <3 x i16> %t3, %t4
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102 ret <3 x i16> %t5
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103 }
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104
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105 ; One-use tests
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106
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107 declare void @use16(i16)
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108 declare void @use32(i32)
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109
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110 define i16 @t6_extrause0(i32 %x, i16 %y) {
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111 ; CHECK-LABEL: @t6_extrause0(
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112 ; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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113 ; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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114 ; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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115 ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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116 ; CHECK-NEXT: call void @use16(i16 [[T3]])
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117 ; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X]] to i16
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118 ; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
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119 ; CHECK-NEXT: ret i16 [[T5]]
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120 ;
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121 %t0 = sub i16 32, %y
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122 %t1 = zext i16 %t0 to i32
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123 %t2 = shl i32 %x, %t1
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124 %t3 = trunc i32 %t2 to i16
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125 %t4 = add i16 %y, -24
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126 call void @use16(i16 %t3)
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127 %t5 = shl i16 %t3, %t4
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128 ret i16 %t5
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129 }
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130
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131 define i16 @t7_extrause1(i32 %x, i16 %y) {
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132 ; CHECK-LABEL: @t7_extrause1(
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133 ; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y:%.*]], -24
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134 ; CHECK-NEXT: call void @use16(i16 [[T4]])
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135 ; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
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136 ; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
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137 ; CHECK-NEXT: ret i16 [[T5]]
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138 ;
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139 %t0 = sub i16 32, %y
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140 %t1 = zext i16 %t0 to i32
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141 %t2 = shl i32 %x, %t1
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142 %t3 = trunc i32 %t2 to i16
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143 %t4 = add i16 %y, -24
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144 call void @use16(i16 %t4)
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145 %t5 = shl i16 %t3, %t4
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146 ret i16 %t5
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147 }
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148
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149 define i16 @t8_extrause2(i32 %x, i16 %y) {
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150 ; CHECK-LABEL: @t8_extrause2(
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151 ; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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152 ; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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153 ; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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154 ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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155 ; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -24
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156 ; CHECK-NEXT: call void @use16(i16 [[T3]])
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157 ; CHECK-NEXT: call void @use16(i16 [[T4]])
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158 ; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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159 ; CHECK-NEXT: ret i16 [[T5]]
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160 ;
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161 %t0 = sub i16 32, %y
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162 %t1 = zext i16 %t0 to i32
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163 %t2 = shl i32 %x, %t1
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164 %t3 = trunc i32 %t2 to i16
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165 %t4 = add i16 %y, -24
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166 call void @use16(i16 %t3)
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167 call void @use16(i16 %t4)
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168 %t5 = shl i16 %t3, %t4
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169 ret i16 %t5
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170 }
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171
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172 ; No 'nuw'/'nsw' flags are to be propagated!
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173 ; But we can't test that, such IR does not reach that code.
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174
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175 ; Negative tests
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176
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177 ; No folding possible for right-shifts..
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178 define i16 @t9_shl(i32 %x, i16 %y) {
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179 ; CHECK-LABEL: @t9_shl(
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180 ; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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181 ; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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182 ; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[X:%.*]], [[T1]]
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183 ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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184 ; CHECK-NEXT: ret i16 [[T3]]
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185 ;
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186 %t0 = sub i16 32, %y
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187 %t1 = zext i16 %t0 to i32
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188 %t2 = lshr i32 %x, %t1
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189 %t3 = trunc i32 %t2 to i16
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190 %t4 = add i16 %y, -24
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191 %t5 = lshr i16 %t3, %t4
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192 ret i16 %t3
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193 }
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194 define i16 @t10_ashr(i32 %x, i16 %y) {
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195 ; CHECK-LABEL: @t10_ashr(
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196 ; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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197 ; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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198 ; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[X:%.*]], [[T1]]
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199 ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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200 ; CHECK-NEXT: ret i16 [[T3]]
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201 ;
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202 %t0 = sub i16 32, %y
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203 %t1 = zext i16 %t0 to i32
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204 %t2 = ashr i32 %x, %t1
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205 %t3 = trunc i32 %t2 to i16
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206 %t4 = add i16 %y, -24
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207 %t5 = ashr i16 %t3, %t4
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208 ret i16 %t3
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209 }
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210
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211 ; Can't fold, total shift would be 32
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212 define i16 @n11(i32 %x, i16 %y) {
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213 ; CHECK-LABEL: @n11(
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214 ; CHECK-NEXT: [[T0:%.*]] = sub i16 30, [[Y:%.*]]
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215 ; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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216 ; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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217 ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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218 ; CHECK-NEXT: ret i16 [[T3]]
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219 ;
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220 %t0 = sub i16 30, %y
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221 %t1 = zext i16 %t0 to i32
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222 %t2 = shl i32 %x, %t1
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223 %t3 = trunc i32 %t2 to i16
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224 %t4 = add i16 %y, -24
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225 %t5 = shl i16 %t3, %t4
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226 ret i16 %t3
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227 }
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228
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229 ; Bit width mismatch of shit amount
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230
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231 @Y32 = global i32 42
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232 @Y16 = global i16 42
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233 define i16 @t01(i32 %x) {
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234 ; CHECK-LABEL: @t01(
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235 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], ptrtoint (i32* @Y32 to i32)
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236 ; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[T0]] to i16
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237 ; CHECK-NEXT: [[T2:%.*]] = shl i16 [[T1]], ptrtoint (i16* @Y16 to i16)
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238 ; CHECK-NEXT: ret i16 [[T2]]
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239 ;
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240 %t0 = shl i32 %x, ptrtoint (i32* @Y32 to i32)
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241 %t1 = trunc i32 %t0 to i16
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242 %t2 = shl i16 %t1, ptrtoint (i16* @Y16 to i16)
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243 ret i16 %t2
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244 }
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