|
147
|
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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0
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2 ; RUN: opt < %s -instcombine -S | FileCheck %s
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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3
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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4 define void @test1(i32* %P) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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5 ; CHECK-LABEL: @test1(
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|
147
|
6 ; CHECK-NEXT: store i32 123, i32* undef, align 4
|
|
|
7 ; CHECK-NEXT: store i32 undef, i32* null, align 536870912
|
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8 ; CHECK-NEXT: ret void
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9 ;
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10 store i32 undef, i32* %P
|
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11 store i32 123, i32* undef
|
|
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12 store i32 124, i32* null
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13 ret void
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0
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parents:
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14 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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15
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 define void @test2(i32* %P) {
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17 ; CHECK-LABEL: @test2(
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147
|
18 ; CHECK-NEXT: ret void
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19 ;
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20 %X = load i32, i32* %P
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21 %Y = add i32 %X, 0
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22 store i32 %Y, i32* %P
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23 ret void
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24 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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25
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134
|
26 define void @store_at_gep_off_null(i64 %offset) {
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147
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27 ; CHECK-LABEL: @store_at_gep_off_null(
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28 ; CHECK-NEXT: [[PTR:%.*]] = getelementptr i32, i32* null, i64 [[OFFSET:%.*]]
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29 ; CHECK-NEXT: store i32 undef, i32* [[PTR]], align 4
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30 ; CHECK-NEXT: ret void
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31 ;
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32 %ptr = getelementptr i32, i32 *null, i64 %offset
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33 store i32 24, i32* %ptr
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34 ret void
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|
134
|
35 }
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36
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147
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37 define void @store_at_gep_off_no_null_opt(i64 %offset) #0 {
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38 ; CHECK-LABEL: @store_at_gep_off_no_null_opt(
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39 ; CHECK-NEXT: [[PTR:%.*]] = getelementptr i32, i32* null, i64 [[OFFSET:%.*]]
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40 ; CHECK-NEXT: store i32 24, i32* [[PTR]], align 4
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41 ; CHECK-NEXT: ret void
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42 ;
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43 %ptr = getelementptr i32, i32 *null, i64 %offset
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44 store i32 24, i32* %ptr
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45 ret void
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46 }
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47
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48 attributes #0 = { "null-pointer-is-valid"="true" }
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49
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50 ;; Simple sinking tests
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51
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52 ; "if then else"
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53 define i32 @test3(i1 %C) {
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147
|
54 ; CHECK-LABEL: @test3(
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55 ; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[COND2:%.*]]
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56 ; CHECK: Cond:
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57 ; CHECK-NEXT: br label [[CONT:%.*]]
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58 ; CHECK: Cond2:
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59 ; CHECK-NEXT: br label [[CONT]]
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60 ; CHECK: Cont:
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61 ; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -987654321, [[COND]] ], [ 47, [[COND2]] ]
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62 ; CHECK-NEXT: ret i32 [[STOREMERGE]]
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63 ;
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64 %A = alloca i32
|
|
|
65 br i1 %C, label %Cond, label %Cond2
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66
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67 Cond:
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147
|
68 store i32 -987654321, i32* %A
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|
|
69 br label %Cont
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70
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71 Cond2:
|
|
147
|
72 store i32 47, i32* %A
|
|
|
73 br label %Cont
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74
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75 Cont:
|
|
147
|
76 %V = load i32, i32* %A
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|
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77 ret i32 %V
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78 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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79
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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80 ; "if then"
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81 define i32 @test4(i1 %C) {
|
|
147
|
82 ; CHECK-LABEL: @test4(
|
|
|
83 ; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[CONT:%.*]]
|
|
|
84 ; CHECK: Cond:
|
|
|
85 ; CHECK-NEXT: br label [[CONT]]
|
|
|
86 ; CHECK: Cont:
|
|
|
87 ; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -987654321, [[COND]] ], [ 47, [[TMP0:%.*]] ]
|
|
|
88 ; CHECK-NEXT: ret i32 [[STOREMERGE]]
|
|
|
89 ;
|
|
|
90 %A = alloca i32
|
|
|
91 store i32 47, i32* %A
|
|
|
92 br i1 %C, label %Cond, label %Cont
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|
93
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parents:
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94 Cond:
|
|
147
|
95 store i32 -987654321, i32* %A
|
|
|
96 br label %Cont
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|
97
|
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parents:
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98 Cont:
|
|
147
|
99 %V = load i32, i32* %A
|
|
|
100 ret i32 %V
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101 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
102
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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103 ; "if then"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
104 define void @test5(i1 %C, i32* %P) {
|
|
147
|
105 ; CHECK-LABEL: @test5(
|
|
|
106 ; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[CONT:%.*]]
|
|
|
107 ; CHECK: Cond:
|
|
|
108 ; CHECK-NEXT: br label [[CONT]]
|
|
|
109 ; CHECK: Cont:
|
|
|
110 ; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -987654321, [[COND]] ], [ 47, [[TMP0:%.*]] ]
|
|
|
111 ; CHECK-NEXT: store i32 [[STOREMERGE]], i32* [[P:%.*]], align 1
|
|
|
112 ; CHECK-NEXT: ret void
|
|
|
113 ;
|
|
|
114 store i32 47, i32* %P, align 1
|
|
|
115 br i1 %C, label %Cond, label %Cont
|
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parents:
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|
116
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
117 Cond:
|
|
147
|
118 store i32 -987654321, i32* %P, align 1
|
|
|
119 br label %Cont
|
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parents:
diff
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|
120
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
121 Cont:
|
|
147
|
122 ret void
|
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parents:
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|
123 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
124
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
125
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
126 ; PR14753 - merging two stores should preserve the TBAA tag.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
127 define void @test6(i32 %n, float* %a, i32* %gi) nounwind uwtable ssp {
|
|
147
|
128 ; CHECK-LABEL: @test6(
|
|
|
129 ; CHECK-NEXT: entry:
|
|
|
130 ; CHECK-NEXT: br label [[FOR_COND:%.*]]
|
|
|
131 ; CHECK: for.cond:
|
|
|
132 ; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 42, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
|
|
|
133 ; CHECK-NEXT: store i32 [[STOREMERGE]], i32* [[GI:%.*]], align 4, !tbaa !0
|
|
|
134 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[STOREMERGE]], [[N:%.*]]
|
|
|
135 ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
|
|
|
136 ; CHECK: for.body:
|
|
|
137 ; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[STOREMERGE]] to i64
|
|
|
138 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[IDXPROM]]
|
|
|
139 ; CHECK-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !tbaa !4
|
|
|
140 ; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[GI]], align 4, !tbaa !0
|
|
|
141 ; CHECK-NEXT: [[INC]] = add nsw i32 [[TMP0]], 1
|
|
|
142 ; CHECK-NEXT: br label [[FOR_COND]]
|
|
|
143 ; CHECK: for.end:
|
|
|
144 ; CHECK-NEXT: ret void
|
|
|
145 ;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
146 entry:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
147 store i32 42, i32* %gi, align 4, !tbaa !0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
148 br label %for.cond
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
149
|
|
147
|
150 for.cond:
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
151 %storemerge = phi i32 [ 0, %entry ], [ %inc, %for.body ]
|
|
95
|
152 %0 = load i32, i32* %gi, align 4, !tbaa !0
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
153 %cmp = icmp slt i32 %0, %n
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
154 br i1 %cmp, label %for.body, label %for.end
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
155
|
|
147
|
156 for.body:
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
157 %idxprom = sext i32 %0 to i64
|
|
95
|
158 %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
159 store float 0.000000e+00, float* %arrayidx, align 4, !tbaa !3
|
|
95
|
160 %1 = load i32, i32* %gi, align 4, !tbaa !0
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
161 %inc = add nsw i32 %1, 1
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
162 store i32 %inc, i32* %gi, align 4, !tbaa !0
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
163 br label %for.cond
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
164
|
|
147
|
165 for.end:
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
166 ret void
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
167 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
168
|
|
100
|
169 define void @dse1(i32* %p) {
|
|
147
|
170 ; CHECK-LABEL: @dse1(
|
|
|
171 ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
|
|
|
172 ; CHECK-NEXT: ret void
|
|
|
173 ;
|
|
100
|
174 store i32 0, i32* %p
|
|
|
175 store i32 0, i32* %p
|
|
|
176 ret void
|
|
147
|
177 }
|
|
100
|
178
|
|
|
179 ; Slightly subtle: if we're mixing atomic and non-atomic access to the
|
|
|
180 ; same location, then the contents of the location are undefined if there's
|
|
147
|
181 ; an actual race. As such, we're free to pick either store under the
|
|
100
|
182 ; assumption that we're not racing with any other thread.
|
|
|
183 define void @dse2(i32* %p) {
|
|
147
|
184 ; CHECK-LABEL: @dse2(
|
|
|
185 ; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
|
|
|
186 ; CHECK-NEXT: ret void
|
|
|
187 ;
|
|
100
|
188 store atomic i32 0, i32* %p unordered, align 4
|
|
|
189 store i32 0, i32* %p
|
|
|
190 ret void
|
|
147
|
191 }
|
|
100
|
192
|
|
|
193 define void @dse3(i32* %p) {
|
|
147
|
194 ; CHECK-LABEL: @dse3(
|
|
|
195 ; CHECK-NEXT: store atomic i32 0, i32* [[P:%.*]] unordered, align 4
|
|
|
196 ; CHECK-NEXT: ret void
|
|
|
197 ;
|
|
100
|
198 store i32 0, i32* %p
|
|
|
199 store atomic i32 0, i32* %p unordered, align 4
|
|
|
200 ret void
|
|
147
|
201 }
|
|
100
|
202
|
|
|
203 define void @dse4(i32* %p) {
|
|
147
|
204 ; CHECK-LABEL: @dse4(
|
|
|
205 ; CHECK-NEXT: store atomic i32 0, i32* [[P:%.*]] unordered, align 4
|
|
|
206 ; CHECK-NEXT: ret void
|
|
|
207 ;
|
|
100
|
208 store atomic i32 0, i32* %p unordered, align 4
|
|
|
209 store atomic i32 0, i32* %p unordered, align 4
|
|
|
210 ret void
|
|
147
|
211 }
|
|
100
|
212
|
|
|
213 ; Implementation limit - could remove unordered store here, but
|
|
|
214 ; currently don't.
|
|
|
215 define void @dse5(i32* %p) {
|
|
147
|
216 ; CHECK-LABEL: @dse5(
|
|
|
217 ; CHECK-NEXT: store atomic i32 0, i32* [[P:%.*]] unordered, align 4
|
|
|
218 ; CHECK-NEXT: store atomic i32 0, i32* [[P]] seq_cst, align 4
|
|
|
219 ; CHECK-NEXT: ret void
|
|
|
220 ;
|
|
100
|
221 store atomic i32 0, i32* %p unordered, align 4
|
|
|
222 store atomic i32 0, i32* %p seq_cst, align 4
|
|
|
223 ret void
|
|
|
224 }
|
|
|
225
|
|
|
226 define void @write_back1(i32* %p) {
|
|
147
|
227 ; CHECK-LABEL: @write_back1(
|
|
|
228 ; CHECK-NEXT: ret void
|
|
|
229 ;
|
|
100
|
230 %v = load i32, i32* %p
|
|
|
231 store i32 %v, i32* %p
|
|
|
232 ret void
|
|
147
|
233 }
|
|
100
|
234
|
|
|
235 define void @write_back2(i32* %p) {
|
|
147
|
236 ; CHECK-LABEL: @write_back2(
|
|
|
237 ; CHECK-NEXT: ret void
|
|
|
238 ;
|
|
100
|
239 %v = load atomic i32, i32* %p unordered, align 4
|
|
|
240 store i32 %v, i32* %p
|
|
|
241 ret void
|
|
147
|
242 }
|
|
100
|
243
|
|
|
244 define void @write_back3(i32* %p) {
|
|
147
|
245 ; CHECK-LABEL: @write_back3(
|
|
|
246 ; CHECK-NEXT: ret void
|
|
|
247 ;
|
|
100
|
248 %v = load i32, i32* %p
|
|
|
249 store atomic i32 %v, i32* %p unordered, align 4
|
|
|
250 ret void
|
|
147
|
251 }
|
|
100
|
252
|
|
|
253 define void @write_back4(i32* %p) {
|
|
147
|
254 ; CHECK-LABEL: @write_back4(
|
|
|
255 ; CHECK-NEXT: ret void
|
|
|
256 ;
|
|
100
|
257 %v = load atomic i32, i32* %p unordered, align 4
|
|
|
258 store atomic i32 %v, i32* %p unordered, align 4
|
|
|
259 ret void
|
|
147
|
260 }
|
|
100
|
261
|
|
|
262 ; Can't remove store due to ordering side effect
|
|
|
263 define void @write_back5(i32* %p) {
|
|
147
|
264 ; CHECK-LABEL: @write_back5(
|
|
|
265 ; CHECK-NEXT: [[V:%.*]] = load atomic i32, i32* [[P:%.*]] unordered, align 4
|
|
|
266 ; CHECK-NEXT: store atomic i32 [[V]], i32* [[P]] seq_cst, align 4
|
|
|
267 ; CHECK-NEXT: ret void
|
|
|
268 ;
|
|
100
|
269 %v = load atomic i32, i32* %p unordered, align 4
|
|
|
270 store atomic i32 %v, i32* %p seq_cst, align 4
|
|
|
271 ret void
|
|
|
272 }
|
|
|
273
|
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274 define void @write_back6(i32* %p) {
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147
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275 ; CHECK-LABEL: @write_back6(
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276 ; CHECK-NEXT: [[V:%.*]] = load atomic i32, i32* [[P:%.*]] seq_cst, align 4
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277 ; CHECK-NEXT: ret void
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278 ;
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100
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279 %v = load atomic i32, i32* %p seq_cst, align 4
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280 store atomic i32 %v, i32* %p unordered, align 4
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281 ret void
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282 }
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283
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284 define void @write_back7(i32* %p) {
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147
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285 ; CHECK-LABEL: @write_back7(
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286 ; CHECK-NEXT: [[V:%.*]] = load atomic volatile i32, i32* [[P:%.*]] seq_cst, align 4
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287 ; CHECK-NEXT: ret void
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288 ;
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100
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289 %v = load atomic volatile i32, i32* %p seq_cst, align 4
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290 store atomic i32 %v, i32* %p unordered, align 4
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291 ret void
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292 }
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293
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147
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294 @Unknown = external constant i32
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295
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296 define void @store_to_constant() {
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297 ; CHECK-LABEL: @store_to_constant(
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298 ; CHECK-NEXT: ret void
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299 ;
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300 store i32 0, i32* @Unknown
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301 ret void
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302 }
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303
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83
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304 !0 = !{!4, !4, i64 0}
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305 !1 = !{!"omnipotent char", !2}
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306 !2 = !{!"Simple C/C++ TBAA"}
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307 !3 = !{!"float", !1}
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308 !4 = !{!"int", !1}
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