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236
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1 // RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -disable-O0-optnone -emit-llvm %s | opt -S -mem2reg | FileCheck %s
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2
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3 // REQUIRES: aarch64-registered-target || arm-registered-target
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150
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4
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5 #include <arm_neon.h>
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6
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7 // vdupq_n_f64 -> dup.2d v0, v0[0]
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8 //
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236
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9 // CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_n_f64(double noundef %w) #0 {
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150
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10 // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0
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11 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1
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12 // CHECK: ret <2 x double> [[VECINIT1_I]]
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13 float64x2_t test_vdupq_n_f64(float64_t w) {
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14 return vdupq_n_f64(w);
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15 }
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16
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17 // might as well test this while we're here
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18 // vdupq_n_f32 -> dup.4s v0, v0[0]
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236
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19 // CHECK-LABEL: define{{.*}} <4 x float> @test_vdupq_n_f32(float noundef %w) #0 {
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150
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20 // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %w, i32 0
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21 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %w, i32 1
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22 // CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %w, i32 2
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23 // CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %w, i32 3
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24 // CHECK: ret <4 x float> [[VECINIT3_I]]
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25 float32x4_t test_vdupq_n_f32(float32_t w) {
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26 return vdupq_n_f32(w);
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27 }
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28
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29 // vdupq_lane_f64 -> dup.2d v0, v0[0]
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30 // this was in <rdar://problem/11778405>, but had already been implemented,
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31 // test anyway
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236
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32 // CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 {
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173
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33 // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %V to <8 x i8>
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34 // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double>
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35 // CHECK: [[SHUFFLE:%.*]] = shufflevector <1 x double> [[TMP1]], <1 x double> [[TMP1]], <2 x i32> zeroinitializer
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150
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36 // CHECK: ret <2 x double> [[SHUFFLE]]
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37 float64x2_t test_vdupq_lane_f64(float64x1_t V) {
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38 return vdupq_lane_f64(V, 0);
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39 }
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40
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41 // vmovq_n_f64 -> dup Vd.2d,X0
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42 // this wasn't in <rdar://problem/11778405>, but it was between the vdups
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236
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43 // CHECK-LABEL: define{{.*}} <2 x double> @test_vmovq_n_f64(double noundef %w) #0 {
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150
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44 // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0
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45 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1
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46 // CHECK: ret <2 x double> [[VECINIT1_I]]
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47 float64x2_t test_vmovq_n_f64(float64_t w) {
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48 return vmovq_n_f64(w);
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49 }
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50
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236
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51 // CHECK-LABEL: define{{.*}} <4 x half> @test_vmov_n_f16(ptr noundef %a1) #1 {
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52 // CHECK: [[TMP0:%.*]] = load half, ptr %a1, align 2
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150
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53 // CHECK: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[TMP0]], i32 0
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54 // CHECK: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 1
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55 // CHECK: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[TMP0]], i32 2
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56 // CHECK: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[TMP0]], i32 3
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57 // CHECK: ret <4 x half> [[VECINIT3]]
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58 float16x4_t test_vmov_n_f16(float16_t *a1) {
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59 return vmov_n_f16(*a1);
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60 }
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61
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62 /*
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63 float64x1_t test_vmov_n_f64(float64_t a1) {
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64 return vmov_n_f64(a1);
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65 }
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66 */
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67
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236
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68 // CHECK-LABEL: define{{.*}} <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 {
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69 // CHECK: [[TMP0:%.*]] = load half, ptr %a1, align 2
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150
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70 // CHECK: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[TMP0]], i32 0
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71 // CHECK: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[TMP0]], i32 1
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72 // CHECK: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[TMP0]], i32 2
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73 // CHECK: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[TMP0]], i32 3
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74 // CHECK: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[TMP0]], i32 4
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75 // CHECK: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[TMP0]], i32 5
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76 // CHECK: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[TMP0]], i32 6
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77 // CHECK: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[TMP0]], i32 7
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78 // CHECK: ret <8 x half> [[VECINIT7]]
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79 float16x8_t test_vmovq_n_f16(float16_t *a1) {
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80 return vmovq_n_f16(*a1);
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81 }
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82
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83 // CHECK: attributes #0 ={{.*}}"min-legal-vector-width"="128"
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84 // CHECK: attributes #1 ={{.*}}"min-legal-vector-width"="64"
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