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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
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3 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
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4 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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236
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5 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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150
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6
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7 ; ===================================================================================
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8 ; V_ADD3_U32
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9 ; ===================================================================================
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10
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11 define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) {
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12 ; VI-LABEL: add3:
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13 ; VI: ; %bb.0:
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14 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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15 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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16 ; VI-NEXT: ; return to shader part epilog
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17 ;
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18 ; GFX9-LABEL: add3:
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19 ; GFX9: ; %bb.0:
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20 ; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
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21 ; GFX9-NEXT: ; return to shader part epilog
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22 ;
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23 ; GFX10-LABEL: add3:
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24 ; GFX10: ; %bb.0:
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25 ; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
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26 ; GFX10-NEXT: ; return to shader part epilog
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27 %x = add i32 %a, %b
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28 %result = add i32 %x, %c
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29 %bc = bitcast i32 %result to float
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30 ret float %bc
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31 }
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32
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33 ; V_MAD_U32_U24 is given higher priority.
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34 define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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35 ; VI-LABEL: mad_no_add3:
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36 ; VI: ; %bb.0:
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37 ; VI-NEXT: v_mad_u32_u24 v0, v0, v1, v4
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38 ; VI-NEXT: v_mad_u32_u24 v0, v2, v3, v0
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39 ; VI-NEXT: ; return to shader part epilog
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40 ;
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41 ; GFX9-LABEL: mad_no_add3:
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42 ; GFX9: ; %bb.0:
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43 ; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v4
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44 ; GFX9-NEXT: v_mad_u32_u24 v0, v2, v3, v0
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45 ; GFX9-NEXT: ; return to shader part epilog
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46 ;
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47 ; GFX10-LABEL: mad_no_add3:
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48 ; GFX10: ; %bb.0:
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49 ; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v4
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50 ; GFX10-NEXT: v_mad_u32_u24 v0, v2, v3, v0
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51 ; GFX10-NEXT: ; return to shader part epilog
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52 %a0 = shl i32 %a, 8
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53 %a1 = lshr i32 %a0, 8
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54 %b0 = shl i32 %b, 8
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55 %b1 = lshr i32 %b0, 8
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56 %mul1 = mul i32 %a1, %b1
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57
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58 %c0 = shl i32 %c, 8
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59 %c1 = lshr i32 %c0, 8
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60 %d0 = shl i32 %d, 8
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61 %d1 = lshr i32 %d0, 8
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62 %mul2 = mul i32 %c1, %d1
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63
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64 %add0 = add i32 %e, %mul1
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65 %add1 = add i32 %mul2, %add0
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66
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67 %bc = bitcast i32 %add1 to float
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68 ret float %bc
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69 }
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70
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71 ; ThreeOp instruction variant not used due to Constant Bus Limitations
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72 ; TODO: with reassociation it is possible to replace a v_add_u32_e32 with a s_add_i32
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73 define amdgpu_ps float @add3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
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74 ; VI-LABEL: add3_vgpr_b:
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75 ; VI: ; %bb.0:
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76 ; VI-NEXT: s_add_i32 s3, s3, s2
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77 ; VI-NEXT: v_add_u32_e32 v0, vcc, s3, v0
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78 ; VI-NEXT: ; return to shader part epilog
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79 ;
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80 ; GFX9-LABEL: add3_vgpr_b:
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81 ; GFX9: ; %bb.0:
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82 ; GFX9-NEXT: s_add_i32 s3, s3, s2
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83 ; GFX9-NEXT: v_add_u32_e32 v0, s3, v0
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84 ; GFX9-NEXT: ; return to shader part epilog
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85 ;
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86 ; GFX10-LABEL: add3_vgpr_b:
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87 ; GFX10: ; %bb.0:
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88 ; GFX10-NEXT: v_add3_u32 v0, s3, s2, v0
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89 ; GFX10-NEXT: ; return to shader part epilog
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90 %x = add i32 %a, %b
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91 %result = add i32 %x, %c
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92 %bc = bitcast i32 %result to float
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93 ret float %bc
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94 }
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95
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96 define amdgpu_ps float @add3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
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97 ; VI-LABEL: add3_vgpr_all2:
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98 ; VI: ; %bb.0:
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99 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
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100 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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101 ; VI-NEXT: ; return to shader part epilog
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102 ;
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103 ; GFX9-LABEL: add3_vgpr_all2:
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104 ; GFX9: ; %bb.0:
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105 ; GFX9-NEXT: v_add3_u32 v0, v1, v2, v0
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106 ; GFX9-NEXT: ; return to shader part epilog
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107 ;
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108 ; GFX10-LABEL: add3_vgpr_all2:
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109 ; GFX10: ; %bb.0:
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110 ; GFX10-NEXT: v_add3_u32 v0, v1, v2, v0
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111 ; GFX10-NEXT: ; return to shader part epilog
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112 %x = add i32 %b, %c
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113 %result = add i32 %a, %x
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114 %bc = bitcast i32 %result to float
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115 ret float %bc
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116 }
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117
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118 define amdgpu_ps float @add3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
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119 ; VI-LABEL: add3_vgpr_bc:
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120 ; VI: ; %bb.0:
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121 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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122 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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123 ; VI-NEXT: ; return to shader part epilog
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124 ;
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125 ; GFX9-LABEL: add3_vgpr_bc:
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126 ; GFX9: ; %bb.0:
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127 ; GFX9-NEXT: v_add3_u32 v0, s2, v0, v1
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128 ; GFX9-NEXT: ; return to shader part epilog
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129 ;
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130 ; GFX10-LABEL: add3_vgpr_bc:
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131 ; GFX10: ; %bb.0:
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132 ; GFX10-NEXT: v_add3_u32 v0, s2, v0, v1
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133 ; GFX10-NEXT: ; return to shader part epilog
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134 %x = add i32 %a, %b
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135 %result = add i32 %x, %c
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136 %bc = bitcast i32 %result to float
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137 ret float %bc
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138 }
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139
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140 define amdgpu_ps float @add3_vgpr_const(i32 %a, i32 %b) {
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141 ; VI-LABEL: add3_vgpr_const:
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142 ; VI: ; %bb.0:
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143 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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144 ; VI-NEXT: v_add_u32_e32 v0, vcc, 16, v0
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145 ; VI-NEXT: ; return to shader part epilog
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146 ;
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147 ; GFX9-LABEL: add3_vgpr_const:
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148 ; GFX9: ; %bb.0:
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149 ; GFX9-NEXT: v_add3_u32 v0, v0, v1, 16
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150 ; GFX9-NEXT: ; return to shader part epilog
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151 ;
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152 ; GFX10-LABEL: add3_vgpr_const:
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153 ; GFX10: ; %bb.0:
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154 ; GFX10-NEXT: v_add3_u32 v0, v0, v1, 16
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155 ; GFX10-NEXT: ; return to shader part epilog
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156 %x = add i32 %a, %b
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157 %result = add i32 %x, 16
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158 %bc = bitcast i32 %result to float
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159 ret float %bc
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160 }
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161
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162 define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) {
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163 ; VI-LABEL: add3_multiuse_outer:
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164 ; VI: ; %bb.0:
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165 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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166 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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167 ; VI-NEXT: v_mul_lo_u32 v1, v0, v3
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168 ; VI-NEXT: ; return to shader part epilog
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169 ;
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170 ; GFX9-LABEL: add3_multiuse_outer:
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171 ; GFX9: ; %bb.0:
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172 ; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
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173 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3
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174 ; GFX9-NEXT: ; return to shader part epilog
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175 ;
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176 ; GFX10-LABEL: add3_multiuse_outer:
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177 ; GFX10: ; %bb.0:
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178 ; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
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179 ; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3
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180 ; GFX10-NEXT: ; return to shader part epilog
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181 %inner = add i32 %a, %b
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182 %outer = add i32 %inner, %c
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183 %x1 = mul i32 %outer, %x
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184 %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
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185 %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
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186 %bc = bitcast <2 x i32> %r0 to <2 x float>
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187 ret <2 x float> %bc
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188 }
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189
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190 define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
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191 ; VI-LABEL: add3_multiuse_inner:
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192 ; VI: ; %bb.0:
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193 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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194 ; VI-NEXT: v_add_u32_e32 v1, vcc, v0, v2
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195 ; VI-NEXT: ; return to shader part epilog
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196 ;
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197 ; GFX9-LABEL: add3_multiuse_inner:
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198 ; GFX9: ; %bb.0:
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199 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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200 ; GFX9-NEXT: v_add_u32_e32 v1, v0, v2
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201 ; GFX9-NEXT: ; return to shader part epilog
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202 ;
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203 ; GFX10-LABEL: add3_multiuse_inner:
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204 ; GFX10: ; %bb.0:
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205 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
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206 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v0, v2
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207 ; GFX10-NEXT: ; return to shader part epilog
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208 %inner = add i32 %a, %b
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209 %outer = add i32 %inner, %c
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210 %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
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211 %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
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212 %bc = bitcast <2 x i32> %r0 to <2 x float>
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213 ret <2 x float> %bc
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214 }
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215
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216 ; A case where uniform values end up in VGPRs -- we could use v_add3_u32 here,
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217 ; but we don't.
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218 define amdgpu_ps float @add3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) {
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219 ; VI-LABEL: add3_uniform_vgpr:
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220 ; VI: ; %bb.0:
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221 ; VI-NEXT: v_add_f32_e64 v0, s2, 1.0
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222 ; VI-NEXT: v_add_f32_e64 v1, s3, 2.0
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236
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223 ; VI-NEXT: v_mov_b32_e32 v2, 0x40400000
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150
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224 ; VI-NEXT: v_add_f32_e32 v2, s4, v2
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225 ; VI-NEXT: v_add_u32_e32 v0, vcc, v1, v0
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236
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226 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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150
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227 ; VI-NEXT: ; return to shader part epilog
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228 ;
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229 ; GFX9-LABEL: add3_uniform_vgpr:
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230 ; GFX9: ; %bb.0:
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231 ; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0
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232 ; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0
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236
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233 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x40400000
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150
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234 ; GFX9-NEXT: v_add_f32_e32 v2, s4, v2
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235 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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236 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
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237 ; GFX9-NEXT: ; return to shader part epilog
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238 ;
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239 ; GFX10-LABEL: add3_uniform_vgpr:
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240 ; GFX10: ; %bb.0:
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173
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241 ; GFX10-NEXT: v_add_f32_e64 v0, s2, 1.0
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150
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242 ; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0
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173
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243 ; GFX10-NEXT: v_add_f32_e64 v2, 0x40400000, s4
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244 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
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245 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
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150
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246 ; GFX10-NEXT: ; return to shader part epilog
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247 %a1 = fadd float %a, 1.0
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248 %b2 = fadd float %b, 2.0
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249 %c3 = fadd float %c, 3.0
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250 %bc.a = bitcast float %a1 to i32
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251 %bc.b = bitcast float %b2 to i32
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252 %bc.c = bitcast float %c3 to i32
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253 %x = add i32 %bc.a, %bc.b
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254 %result = add i32 %x, %bc.c
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255 %bc = bitcast i32 %result to float
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256 ret float %bc
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257 }
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