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150
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1 ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tahiti | FileCheck --check-prefixes=PAL,CI --enable-var-scope %s
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2 ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefixes=PAL,VI --enable-var-scope %s
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3
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4 ; PAL-NOT: .AMDGPU.config
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5 ; PAL-LABEL: {{^}}simple:
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6 define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
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7 entry:
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8 store i32 0, i32 addrspace(1)* %out
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9 ret void
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10 }
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11
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12 ; Check code sequence for amdpal use of scratch for alloca. This is the case
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13 ; where the high half of the address comes from s_getpc.
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14
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15 ; PAL-LABEL: {{^}}scratch:
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236
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16 ; PAL: s_getpc_b64 s[[[GITPTR:[0-9]+]]:
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150
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17 ; PAL: s_mov_b32 s[[GITPTR]], s0
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236
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18 ; PAL: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:
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19 ; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
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150
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20
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21 define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) {
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22 entry:
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23 %v = alloca [2 x i32], addrspace(5)
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24 %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
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25 store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
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26 %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
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27 %x = load i32, i32 addrspace(5)* %e
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28 store i32 %x, i32 addrspace(5)* %out
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29 ret void
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30 }
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31
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32 ; Check code sequence for amdpal use of scratch for alloca. This is the case
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33 ; where the amdgpu-git-ptr-high function attribute gives the high half of the
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34 ; address to use.
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35 ; Looks like you can't do arithmetic on a filecheck variable, so we can't test
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36 ; that the s_movk_i32 is into a reg that is one more than the following
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37 ; s_mov_b32.
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38
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39 ; PAL-LABEL: {{^}}scratch2:
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40 ; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
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41 ; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
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236
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42 ; PAL: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:
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43 ; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
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150
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44
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45 define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) #0 {
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46 entry:
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47 %v = alloca [2 x i32], addrspace(5)
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48 %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
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49 store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
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50 %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
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51 %x = load i32, i32 addrspace(5)* %e
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52 store i32 %x, i32 addrspace(5)* %out
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53 ret void
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54 }
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55
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56 ; Check code sequence for amdpal use of scratch for alloca in a compute shader.
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57 ; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset
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58 ; 0 in a graphics shader.
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59 ; Prior to GCN3 s_load_dword offsets are dwords, so the offset will be 0x4.
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60
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61 ; PAL-LABEL: {{^}}scratch2_cs:
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62 ; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
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63 ; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
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236
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64 ; CI: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:{{[0-9]+\]}}, 0x4
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65 ; VI: s_load_dwordx4 s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s[[[GITPTR]]:{{[0-9]+\]}}, 0x10
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66 ; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
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150
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67
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68 define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 {
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69 entry:
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70 %v = alloca [3 x i32], addrspace(5)
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71 %v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0
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72 %v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1
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73 store i32 %extra, i32 addrspace(5)* %v0
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74 %v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)*
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75 %vv = bitcast [2 x i32] addrspace(5)* %v1a to <2 x i32> addrspace(5)*
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76 store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
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77 %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v1a, i32 0, i32 %idx
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78 %x = load i32, i32 addrspace(5)* %e
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79 %xf = bitcast i32 %x to float
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80 call void @llvm.amdgcn.raw.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i32 0)
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81 ret void
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82 }
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83
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84 attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
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85
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86 declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg)
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87
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88
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221
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89 ; PAL: .amdgpu_pal_metadata
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90 ; PAL-NEXT: ---
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91 ; PAL-NEXT: amdpal.pipelines:
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92 ; PAL-NEXT: - .hardware_stages:
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93 ; PAL-NEXT: .cs:
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94 ; PAL-NEXT: .entry_point: scratch2_cs
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95 ; PAL-NEXT: .scratch_memory_size: 0x10
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96 ; PAL-NEXT: .sgpr_count: 0x
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97 ; PAL-NEXT: .vgpr_count: 0x
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