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annotate llvm/test/CodeGen/AMDGPU/hsa.ll @ 236:c4bab56944e8 llvm-original

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LLVM 16
author kono
date Wed, 09 Nov 2022 17:45:10 +0900
parents 5f17cb93ff66
children 1f2b6ac9f198
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221
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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1 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
2 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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3 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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4 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s
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5f17cb93ff66 LLVM13 (2021/7/18)
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 221
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5 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck --check-prefix=ELF %s
5f17cb93ff66 LLVM13 (2021/7/18)
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 221
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6 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck %s --check-prefix=ELF
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
7 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
diff changeset
8 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
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c4bab56944e8 LLVM 16
kono
parents: 223
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9 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
c4bab56944e8 LLVM 16
kono
parents: 223
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10 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
150
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11
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12 ; The SHT_NOTE section contains the output from the .hsa_code_object_*
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13 ; directives.
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14
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15 ; ELF: Section {
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16 ; ELF: Name: .text
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17 ; ELF: Type: SHT_PROGBITS (0x1)
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18 ; ELF: Flags [ (0x6)
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19 ; ELF: SHF_ALLOC (0x2)
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20 ; ELF: SHF_EXECINSTR (0x4)
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21 ; ELF: }
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22
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23 ; ELF: SHT_NOTE
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24 ; ELF: Flags [ (0x2)
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25 ; ELF: SHF_ALLOC (0x2)
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26 ; ELF: ]
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27 ; ELF: SectionData (
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28 ; ELF: 0000: 04000000 08000000 01000000 414D4400
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29 ; ELF: 0010: 02000000 01000000 04000000 1B000000
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30 ; ELF: 0020: 03000000 414D4400 04000700 07000000
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31 ; ELF: 0030: 00000000 00000000 414D4400 414D4447
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32 ; ELF: 0040: 50550000
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33 ; ELF: )
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34
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35 ; ELF: Symbol {
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36 ; ELF: Name: simple
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37 ; ELF: Size: 288
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38 ; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
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39 ; ELF: }
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40
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41 ; HSA-NOT: .AMDGPU.config
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42 ; HSA: .text
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43 ; HSA: .hsa_code_object_version 2,1
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44 ; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
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45 ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
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46
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47 ; HSA-LABEL: .amdgpu_hsa_kernel simple
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48 ; HSA: {{^}}simple:
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49 ; HSA: .amd_kernel_code_t
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50 ; HSA: enable_sgpr_private_segment_buffer = 1
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51 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
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52
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53 ; PRE-GFX10: enable_wavefront_size32 = 0
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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54 ; GFX10-W32: .amdhsa_wavefront_size32 1
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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55 ; GFX10-W64: .amdhsa_wavefront_size32 0
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56
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57 ; PRE-GFX10: wavefront_size = 6
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58
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59 ; HSA: call_convention = -1
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60 ; HSA: .end_amd_kernel_code_t
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c4bab56944e8 LLVM 16
kono
parents: 223
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61 ; HSA: s_load_{{dwordx2|b64}} s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
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62
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63 ; Make sure we are setting the ATC bit:
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64 ; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
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65 ; On VI+ we also need to set MTYPE = 2
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66 ; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
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67 ; Make sure we generate flat store for HSA
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68 ; PRE-GFX10: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
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c4bab56944e8 LLVM 16
kono
parents: 223
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69 ; GFX10: global_store_{{dword|b32}} v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off
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70
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71 ; HSA: .Lfunc_end0:
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72 ; HSA: .size simple, .Lfunc_end0-simple
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73
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74 define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
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75 entry:
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76 store i32 0, i32 addrspace(1)* %out
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77 ret void
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78 }
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79
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80 ; HSA-LABEL: .amdgpu_hsa_kernel simple_no_kernargs
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81 ; HSA: enable_sgpr_kernarg_segment_ptr = 0
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82 define amdgpu_kernel void @simple_no_kernargs() {
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83 entry:
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84 store volatile i32 0, i32 addrspace(1)* undef
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85 ret void
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86 }