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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
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3 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
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4 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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236
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5 ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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150
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6
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7 ; ===================================================================================
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8 ; V_LSHL_ADD_U32
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9 ; ===================================================================================
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10
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11 define amdgpu_ps float @shl_add(i32 %a, i32 %b, i32 %c) {
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12 ; VI-LABEL: shl_add:
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13 ; VI: ; %bb.0:
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14 ; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
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15 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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16 ; VI-NEXT: ; return to shader part epilog
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17 ;
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18 ; GFX9-LABEL: shl_add:
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19 ; GFX9: ; %bb.0:
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20 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
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21 ; GFX9-NEXT: ; return to shader part epilog
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22 ;
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23 ; GFX10-LABEL: shl_add:
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24 ; GFX10: ; %bb.0:
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25 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
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26 ; GFX10-NEXT: ; return to shader part epilog
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27 %x = shl i32 %a, %b
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28 %result = add i32 %x, %c
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29 %bc = bitcast i32 %result to float
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30 ret float %bc
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31 }
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32
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33 ; ThreeOp instruction variant not used due to Constant Bus Limitations
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34 define amdgpu_ps float @shl_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
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35 ; VI-LABEL: shl_add_vgpr_a:
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36 ; VI: ; %bb.0:
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37 ; VI-NEXT: v_lshlrev_b32_e32 v0, s2, v0
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38 ; VI-NEXT: v_add_u32_e32 v0, vcc, s3, v0
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39 ; VI-NEXT: ; return to shader part epilog
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40 ;
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41 ; GFX9-LABEL: shl_add_vgpr_a:
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42 ; GFX9: ; %bb.0:
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43 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, s2, v0
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44 ; GFX9-NEXT: v_add_u32_e32 v0, s3, v0
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45 ; GFX9-NEXT: ; return to shader part epilog
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46 ;
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47 ; GFX10-LABEL: shl_add_vgpr_a:
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48 ; GFX10: ; %bb.0:
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49 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
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50 ; GFX10-NEXT: ; return to shader part epilog
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51 %x = shl i32 %a, %b
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52 %result = add i32 %x, %c
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53 %bc = bitcast i32 %result to float
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54 ret float %bc
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55 }
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56
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57 define amdgpu_ps float @shl_add_vgpr_all(i32 %a, i32 %b, i32 %c) {
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58 ; VI-LABEL: shl_add_vgpr_all:
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59 ; VI: ; %bb.0:
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60 ; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
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61 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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62 ; VI-NEXT: ; return to shader part epilog
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63 ;
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64 ; GFX9-LABEL: shl_add_vgpr_all:
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65 ; GFX9: ; %bb.0:
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66 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
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67 ; GFX9-NEXT: ; return to shader part epilog
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68 ;
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69 ; GFX10-LABEL: shl_add_vgpr_all:
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70 ; GFX10: ; %bb.0:
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71 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
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72 ; GFX10-NEXT: ; return to shader part epilog
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73 %x = shl i32 %a, %b
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74 %result = add i32 %x, %c
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75 %bc = bitcast i32 %result to float
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76 ret float %bc
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77 }
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78
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79 define amdgpu_ps float @shl_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
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80 ; VI-LABEL: shl_add_vgpr_ab:
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81 ; VI: ; %bb.0:
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82 ; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
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83 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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84 ; VI-NEXT: ; return to shader part epilog
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85 ;
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86 ; GFX9-LABEL: shl_add_vgpr_ab:
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87 ; GFX9: ; %bb.0:
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88 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
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89 ; GFX9-NEXT: ; return to shader part epilog
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90 ;
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91 ; GFX10-LABEL: shl_add_vgpr_ab:
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92 ; GFX10: ; %bb.0:
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93 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
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94 ; GFX10-NEXT: ; return to shader part epilog
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95 %x = shl i32 %a, %b
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96 %result = add i32 %x, %c
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97 %bc = bitcast i32 %result to float
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98 ret float %bc
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99 }
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100
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101 define amdgpu_ps float @shl_add_vgpr_const(i32 %a, i32 %b) {
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102 ; VI-LABEL: shl_add_vgpr_const:
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103 ; VI: ; %bb.0:
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104 ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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105 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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106 ; VI-NEXT: ; return to shader part epilog
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107 ;
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108 ; GFX9-LABEL: shl_add_vgpr_const:
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109 ; GFX9: ; %bb.0:
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110 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
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111 ; GFX9-NEXT: ; return to shader part epilog
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112 ;
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113 ; GFX10-LABEL: shl_add_vgpr_const:
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114 ; GFX10: ; %bb.0:
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115 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
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116 ; GFX10-NEXT: ; return to shader part epilog
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117 %x = shl i32 %a, 3
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118 %result = add i32 %x, %b
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119 %bc = bitcast i32 %result to float
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120 ret float %bc
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121 }
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