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1 // RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \
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2 // RUN: FileCheck --check-prefix=COMPRESS %s
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3
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4 // Check that combining conditions in AssemblerPredicate generates the correct
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5 // output when using both the (all_of) AND operator, and the (any_of) OR
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6 // operator in the RISC-V specific instruction compressor.
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7
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8 include "llvm/Target/Target.td"
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9
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10 def archInstrInfo : InstrInfo { }
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11 def archAsmWriter : AsmWriter {
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12 int PassSubtarget = 1;
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13 }
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14
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15 def arch : Target {
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16 let InstructionSet = archInstrInfo;
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17 let AssemblyWriters = [archAsmWriter];
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18 }
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19
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20 let Namespace = "arch" in {
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21 def R0 : Register<"r0">;
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22 }
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23 def Regs : RegisterClass<"Regs", [i32], 32, (add R0)>;
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24
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25 class RVInst<int Opc, list<Predicate> Preds> : Instruction {
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26 let Size = 4;
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27 let OutOperandList = (outs);
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28 let InOperandList = (ins Regs:$r);
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29 field bits<32> Inst;
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30 let Inst = Opc;
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31 let AsmString = NAME # " $r";
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32 field bits<32> SoftFail = 0;
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33 let Predicates = Preds;
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34 }
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35 class RVInst16<int Opc, list<Predicate> Preds> : Instruction {
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36 let Size = 2;
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37 let OutOperandList = (outs);
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38 let InOperandList = (ins Regs:$r);
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39 field bits<16> Inst;
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40 let Inst = Opc;
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41 let AsmString = NAME # " $r";
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42 field bits<16> SoftFail = 0;
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43 let Predicates = Preds;
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44 }
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45
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46 def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
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47 def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
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48 def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
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49 def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
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50 def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
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51
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52 def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
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53 def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
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54 def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
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55
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56 def BigInst : RVInst<1, [AsmPred1]>;
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57
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58 // COMPRESS-LABEL: static bool compressInst
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59 // COMPRESS: case arch::BigInst
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60 def SmallInst1 : RVInst16<1, []>;
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61 def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;
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62 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
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236
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63 // COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
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173
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64 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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65 // COMPRESS-NEXT: // SmallInst1 $r
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66
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67 def SmallInst2 : RVInst16<2, []>;
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68 def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;
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69 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&
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70 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
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236
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71 // COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
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173
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72 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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73 // COMPRESS-NEXT: // SmallInst2 $r
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74
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75 def SmallInst3 : RVInst16<2, []>;
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76 def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;
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77 // COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
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236
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78 // COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
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173
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79 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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80 // COMPRESS-NEXT: // SmallInst3 $r
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81
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82 def SmallInst4 : RVInst16<2, []>;
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83 def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>;
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84 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
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85 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&
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86 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
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236
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87 // COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
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173
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88 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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89 // COMPRESS-NEXT: // SmallInst4 $r
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90
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91 def SmallInst5 : RVInst16<2, []>;
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92 def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;
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93 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
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94 // COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
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236
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95 // COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
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173
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96 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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97 // COMPRESS-NEXT: // SmallInst5 $r
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98
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99 // COMPRESS-LABEL: static bool uncompressInst
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