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1 //===--------------- PPCVSXFMAMutate.cpp - VSX FMA Mutation ---------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This pass mutates the form of VSX FMA instructions to avoid unnecessary
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11 // copies.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 #include "MCTargetDesc/PPCPredicates.h"
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16 #include "PPC.h"
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17 #include "PPCInstrBuilder.h"
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121
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18 #include "PPCInstrInfo.h"
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83
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19 #include "PPCMachineFunctionInfo.h"
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20 #include "PPCTargetMachine.h"
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21 #include "llvm/ADT/STLExtras.h"
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22 #include "llvm/ADT/Statistic.h"
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134
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23 #include "llvm/CodeGen/LiveIntervals.h"
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121
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24 #include "llvm/CodeGen/MachineDominators.h"
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83
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25 #include "llvm/CodeGen/MachineFrameInfo.h"
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26 #include "llvm/CodeGen/MachineFunctionPass.h"
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27 #include "llvm/CodeGen/MachineInstrBuilder.h"
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28 #include "llvm/CodeGen/MachineMemOperand.h"
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29 #include "llvm/CodeGen/MachineRegisterInfo.h"
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30 #include "llvm/CodeGen/PseudoSourceValue.h"
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31 #include "llvm/CodeGen/ScheduleDAG.h"
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32 #include "llvm/CodeGen/SlotIndexes.h"
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33 #include "llvm/MC/MCAsmInfo.h"
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34 #include "llvm/Support/CommandLine.h"
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35 #include "llvm/Support/Debug.h"
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36 #include "llvm/Support/ErrorHandling.h"
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37 #include "llvm/Support/TargetRegistry.h"
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38 #include "llvm/Support/raw_ostream.h"
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39
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40 using namespace llvm;
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41
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120
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42 // Temporarily disable FMA mutation by default, since it doesn't handle
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43 // cross-basic-block intervals well.
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44 // See: http://lists.llvm.org/pipermail/llvm-dev/2016-February/095669.html
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45 // http://reviews.llvm.org/D17087
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46 static cl::opt<bool> DisableVSXFMAMutate(
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47 "disable-ppc-vsx-fma-mutation",
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48 cl::desc("Disable VSX FMA instruction mutation"), cl::init(true),
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49 cl::Hidden);
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83
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50
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51 #define DEBUG_TYPE "ppc-vsx-fma-mutate"
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52
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53 namespace llvm { namespace PPC {
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54 int getAltVSXFMAOpcode(uint16_t Opcode);
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55 } }
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56
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57 namespace {
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58 // PPCVSXFMAMutate pass - For copies between VSX registers and non-VSX registers
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59 // (Altivec and scalar floating-point registers), we need to transform the
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60 // copies into subregister copies with other restrictions.
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61 struct PPCVSXFMAMutate : public MachineFunctionPass {
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62 static char ID;
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63 PPCVSXFMAMutate() : MachineFunctionPass(ID) {
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64 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
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65 }
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66
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67 LiveIntervals *LIS;
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68 const PPCInstrInfo *TII;
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69
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70 protected:
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71 bool processBlock(MachineBasicBlock &MBB) {
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72 bool Changed = false;
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73
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74 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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75 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
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76 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
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77 I != IE; ++I) {
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120
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78 MachineInstr &MI = *I;
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83
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79
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80 // The default (A-type) VSX FMA form kills the addend (it is taken from
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81 // the target register, which is then updated to reflect the result of
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82 // the FMA). If the instruction, however, kills one of the registers
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83 // used for the product, then we can use the M-form instruction (which
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84 // will take that value from the to-be-defined register).
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85
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120
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86 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
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83
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87 if (AltOpc == -1)
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88 continue;
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89
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90 // This pass is run after register coalescing, and so we're looking for
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91 // a situation like this:
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92 // ...
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134
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93 // %5 = COPY %9; VSLRC:%5,%9
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94 // %5<def,tied1> = XSMADDADP %5<tied0>, %17, %16,
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95 // implicit %rm; VSLRC:%5,%17,%16
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83
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96 // ...
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134
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97 // %9<def,tied1> = XSMADDADP %9<tied0>, %17, %19,
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98 // implicit %rm; VSLRC:%9,%17,%19
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83
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99 // ...
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100 // Where we can eliminate the copy by changing from the A-type to the
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101 // M-type instruction. Specifically, for this example, this means:
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134
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102 // %5<def,tied1> = XSMADDADP %5<tied0>, %17, %16,
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103 // implicit %rm; VSLRC:%5,%17,%16
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83
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104 // is replaced by:
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134
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105 // %16<def,tied1> = XSMADDMDP %16<tied0>, %18, %9,
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106 // implicit %rm; VSLRC:%16,%18,%9
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107 // and we remove: %5 = COPY %9; VSLRC:%5,%9
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83
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108
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109 SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
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110
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111 VNInfo *AddendValNo =
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120
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112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn();
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95
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113
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114 // This can be null if the register is undef.
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115 if (!AddendValNo)
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116 continue;
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117
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118 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def);
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119
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120 // The addend and this instruction must be in the same block.
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121
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120
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122 if (!AddendMI || AddendMI->getParent() != MI.getParent())
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83
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123 continue;
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124
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125 // The addend must be a full copy within the same register class.
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126
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127 if (!AddendMI->isFullCopy())
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128 continue;
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129
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130 unsigned AddendSrcReg = AddendMI->getOperand(1).getReg();
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131 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg)) {
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132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
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133 MRI.getRegClass(AddendSrcReg))
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134 continue;
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135 } else {
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136 // If AddendSrcReg is a physical register, make sure the destination
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137 // register class contains it.
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138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
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139 ->contains(AddendSrcReg))
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140 continue;
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141 }
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142
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143 // In theory, there could be other uses of the addend copy before this
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144 // fma. We could deal with this, but that would require additional
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145 // logic below and I suspect it will not occur in any relevant
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146 // situations. Additionally, check whether the copy source is killed
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147 // prior to the fma. In order to replace the addend here with the
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148 // source of the copy, it must still be live here. We can't use
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149 // interval testing for a physical register, so as long as we're
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150 // walking the MIs we may as well test liveness here.
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95
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151 //
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152 // FIXME: There is a case that occurs in practice, like this:
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134
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153 // %9 = COPY %f1; VSSRC:%9
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95
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154 // ...
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134
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155 // %6 = COPY %9; VSSRC:%6,%9
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156 // %7 = COPY %9; VSSRC:%7,%9
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157 // %9<def,tied1> = XSMADDASP %9<tied0>, %1, %4; VSSRC:
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158 // %6<def,tied1> = XSMADDASP %6<tied0>, %1, %2; VSSRC:
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159 // %7<def,tied1> = XSMADDASP %7<tied0>, %1, %3; VSSRC:
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95
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160 // which prevents an otherwise-profitable transformation.
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83
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161 bool OtherUsers = false, KillsAddendSrc = false;
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162 for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI);
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163 J != JE; --J) {
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164 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
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165 OtherUsers = true;
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166 break;
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167 }
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168 if (J->modifiesRegister(AddendSrcReg, TRI) ||
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169 J->killsRegister(AddendSrcReg, TRI)) {
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170 KillsAddendSrc = true;
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171 break;
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172 }
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173 }
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174
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175 if (OtherUsers || KillsAddendSrc)
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176 continue;
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177
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120
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178
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179 // The transformation doesn't work well with things like:
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134
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180 // %5 = A-form-op %5, %11, %5;
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181 // unless %11 is also a kill, so skip when it is not,
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120
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182 // and check operand 3 to see it is also a kill to handle the case:
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134
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183 // %5 = A-form-op %5, %5, %11;
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184 // where %5 and %11 are both kills. This case would be skipped
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120
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185 // otherwise.
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186 unsigned OldFMAReg = MI.getOperand(0).getReg();
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187
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83
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188 // Find one of the product operands that is killed by this instruction.
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189 unsigned KilledProdOp = 0, OtherProdOp = 0;
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120
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190 unsigned Reg2 = MI.getOperand(2).getReg();
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191 unsigned Reg3 = MI.getOperand(3).getReg();
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192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill()
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193 && Reg2 != OldFMAReg) {
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83
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194 KilledProdOp = 2;
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195 OtherProdOp = 3;
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120
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196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill()
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197 && Reg3 != OldFMAReg) {
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83
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198 KilledProdOp = 3;
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199 OtherProdOp = 2;
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200 }
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201
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120
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202 // If there are no usable killed product operands, then this
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203 // transformation is likely not profitable.
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83
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204 if (!KilledProdOp)
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205 continue;
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206
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95
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207 // If the addend copy is used only by this MI, then the addend source
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208 // register is likely not live here. This could be fixed (based on the
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209 // legality checks above, the live range for the addend source register
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210 // could be extended), but it seems likely that such a trivial copy can
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211 // be coalesced away later, and thus is not worth the effort.
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212 if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg) &&
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213 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
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214 continue;
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83
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215
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216 // Transform: (O2 * O3) + O1 -> (O2 * O1) + O3.
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217
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120
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218 unsigned KilledProdReg = MI.getOperand(KilledProdOp).getReg();
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219 unsigned OtherProdReg = MI.getOperand(OtherProdOp).getReg();
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220
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221 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
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120
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222 unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg();
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223 unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg();
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83
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224
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225 bool AddRegKill = AddendMI->getOperand(1).isKill();
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120
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226 bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill();
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227 bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill();
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228
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229 bool AddRegUndef = AddendMI->getOperand(1).isUndef();
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120
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230 bool KilledProdRegUndef = MI.getOperand(KilledProdOp).isUndef();
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231 bool OtherProdRegUndef = MI.getOperand(OtherProdOp).isUndef();
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83
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232
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100
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233 // If there isn't a class that fits, we can't perform the transform.
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234 // This is needed for correctness with a mixture of VSX and Altivec
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235 // instructions to make sure that a low VSX register is not assigned to
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236 // the Altivec instruction.
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237 if (!MRI.constrainRegClass(KilledProdReg,
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238 MRI.getRegClass(OldFMAReg)))
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239 continue;
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240
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83
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241 assert(OldFMAReg == AddendMI->getOperand(0).getReg() &&
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242 "Addend copy not tied to old FMA output!");
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243
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120
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244 DEBUG(dbgs() << "VSX FMA Mutation:\n " << MI);
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245
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246 MI.getOperand(0).setReg(KilledProdReg);
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247 MI.getOperand(1).setReg(KilledProdReg);
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248 MI.getOperand(3).setReg(AddendSrcReg);
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83
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249
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120
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250 MI.getOperand(0).setSubReg(KilledProdSubReg);
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251 MI.getOperand(1).setSubReg(KilledProdSubReg);
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252 MI.getOperand(3).setSubReg(AddSubReg);
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253
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120
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254 MI.getOperand(1).setIsKill(KilledProdRegKill);
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255 MI.getOperand(3).setIsKill(AddRegKill);
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256
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257 MI.getOperand(1).setIsUndef(KilledProdRegUndef);
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258 MI.getOperand(3).setIsUndef(AddRegUndef);
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83
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259
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120
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260 MI.setDesc(TII->get(AltOpc));
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83
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261
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120
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262 // If the addend is also a multiplicand, replace it with the addend
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263 // source in both places.
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264 if (OtherProdReg == AddendMI->getOperand(0).getReg()) {
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265 MI.getOperand(2).setReg(AddendSrcReg);
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266 MI.getOperand(2).setSubReg(AddSubReg);
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267 MI.getOperand(2).setIsKill(AddRegKill);
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268 MI.getOperand(2).setIsUndef(AddRegUndef);
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269 } else {
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270 MI.getOperand(2).setReg(OtherProdReg);
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271 MI.getOperand(2).setSubReg(OtherProdSubReg);
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272 MI.getOperand(2).setIsKill(OtherProdRegKill);
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273 MI.getOperand(2).setIsUndef(OtherProdRegUndef);
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274 }
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83
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275
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120
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276 DEBUG(dbgs() << " -> " << MI);
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83
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277
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278 // The killed product operand was killed here, so we can reuse it now
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279 // for the result of the fma.
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280
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281 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg);
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282 VNInfo *FMAValNo = FMAInt.getVNInfoAt(FMAIdx.getRegSlot());
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283 for (auto UI = MRI.reg_nodbg_begin(OldFMAReg), UE = MRI.reg_nodbg_end();
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284 UI != UE;) {
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285 MachineOperand &UseMO = *UI;
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286 MachineInstr *UseMI = UseMO.getParent();
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287 ++UI;
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288
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289 // Don't replace the result register of the copy we're about to erase.
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290 if (UseMI == AddendMI)
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291 continue;
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292
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100
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293 UseMO.substVirtReg(KilledProdReg, KilledProdSubReg, *TRI);
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83
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294 }
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295
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296 // Extend the live intervals of the killed product operand to hold the
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297 // fma result.
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298
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299 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg);
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300 for (LiveInterval::iterator AI = FMAInt.begin(), AE = FMAInt.end();
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301 AI != AE; ++AI) {
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302 // Don't add the segment that corresponds to the original copy.
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303 if (AI->valno == AddendValNo)
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304 continue;
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305
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306 VNInfo *NewFMAValNo =
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307 NewFMAInt.getNextValue(AI->start,
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308 LIS->getVNInfoAllocator());
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309
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310 NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end,
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311 NewFMAValNo));
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312 }
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313 DEBUG(dbgs() << " extended: " << NewFMAInt << '\n');
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314
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95
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315 // Extend the live interval of the addend source (it might end at the
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316 // copy to be removed, or somewhere in between there and here). This
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317 // is necessary only if it is a physical register.
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318 if (!TargetRegisterInfo::isVirtualRegister(AddendSrcReg))
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319 for (MCRegUnitIterator Units(AddendSrcReg, TRI); Units.isValid();
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320 ++Units) {
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321 unsigned Unit = *Units;
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322
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323 LiveRange &AddendSrcRange = LIS->getRegUnit(Unit);
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324 AddendSrcRange.extendInBlock(LIS->getMBBStartIdx(&MBB),
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325 FMAIdx.getRegSlot());
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326 DEBUG(dbgs() << " extended: " << AddendSrcRange << '\n');
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327 }
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328
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83
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329 FMAInt.removeValNo(FMAValNo);
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330 DEBUG(dbgs() << " trimmed: " << FMAInt << '\n');
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331
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332 // Remove the (now unused) copy.
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333
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334 DEBUG(dbgs() << " removing: " << *AddendMI << '\n');
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120
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335 LIS->RemoveMachineInstrFromMaps(*AddendMI);
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83
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336 AddendMI->eraseFromParent();
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337
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338 Changed = true;
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339 }
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340
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341 return Changed;
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342 }
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343
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344 public:
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345 bool runOnMachineFunction(MachineFunction &MF) override {
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134
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346 if (skipFunction(MF.getFunction()))
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120
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347 return false;
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348
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83
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349 // If we don't have VSX then go ahead and return without doing
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350 // anything.
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351 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
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352 if (!STI.hasVSX())
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353 return false;
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354
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355 LIS = &getAnalysis<LiveIntervals>();
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356
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357 TII = STI.getInstrInfo();
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358
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359 bool Changed = false;
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360
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361 if (DisableVSXFMAMutate)
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362 return Changed;
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363
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364 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
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365 MachineBasicBlock &B = *I++;
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366 if (processBlock(B))
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367 Changed = true;
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368 }
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369
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370 return Changed;
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371 }
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372
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373 void getAnalysisUsage(AnalysisUsage &AU) const override {
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374 AU.addRequired<LiveIntervals>();
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375 AU.addPreserved<LiveIntervals>();
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376 AU.addRequired<SlotIndexes>();
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377 AU.addPreserved<SlotIndexes>();
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121
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378 AU.addRequired<MachineDominatorTree>();
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379 AU.addPreserved<MachineDominatorTree>();
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83
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380 MachineFunctionPass::getAnalysisUsage(AU);
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381 }
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382 };
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383 }
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384
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385 INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE,
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386 "PowerPC VSX FMA Mutation", false, false)
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387 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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388 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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121
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389 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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83
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390 INITIALIZE_PASS_END(PPCVSXFMAMutate, DEBUG_TYPE,
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391 "PowerPC VSX FMA Mutation", false, false)
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392
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393 char &llvm::PPCVSXFMAMutateID = PPCVSXFMAMutate::ID;
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394
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395 char PPCVSXFMAMutate::ID = 0;
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95
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396 FunctionPass *llvm::createPPCVSXFMAMutatePass() {
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397 return new PPCVSXFMAMutate();
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398 }
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