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1 //===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 /// \file
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10 /// This file implements the targeting of the Machinelegalizer class for X86.
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11 /// \todo This should be generated by TableGen.
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "X86LegalizerInfo.h"
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15 #include "X86Subtarget.h"
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16 #include "X86TargetMachine.h"
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134
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17 #include "llvm/CodeGen/TargetOpcodes.h"
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121
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18 #include "llvm/CodeGen/ValueTypes.h"
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19 #include "llvm/IR/DerivedTypes.h"
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20 #include "llvm/IR/Type.h"
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21
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22 using namespace llvm;
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23 using namespace TargetOpcode;
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134
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24 using namespace LegalizeActions;
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25
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26 /// FIXME: The following static functions are SizeChangeStrategy functions
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27 /// that are meant to temporarily mimic the behaviour of the old legalization
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28 /// based on doubling/halving non-legal types as closely as possible. This is
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29 /// not entirly possible as only legalizing the types that are exactly a power
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30 /// of 2 times the size of the legal types would require specifying all those
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31 /// sizes explicitly.
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32 /// In practice, not specifying those isn't a problem, and the below functions
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33 /// should disappear quickly as we add support for legalizing non-power-of-2
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34 /// sized types further.
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35 static void
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36 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
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37 const LegalizerInfo::SizeAndActionsVec &v) {
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38 for (unsigned i = 0; i < v.size(); ++i) {
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39 result.push_back(v[i]);
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40 if (i + 1 < v[i].first && i + 1 < v.size() &&
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41 v[i + 1].first != v[i].first + 1)
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42 result.push_back({v[i].first + 1, Unsupported});
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43 }
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44 }
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45
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46 static LegalizerInfo::SizeAndActionsVec
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47 widen_1(const LegalizerInfo::SizeAndActionsVec &v) {
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48 assert(v.size() >= 1);
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49 assert(v[0].first > 1);
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50 LegalizerInfo::SizeAndActionsVec result = {{1, WidenScalar},
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51 {2, Unsupported}};
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52 addAndInterleaveWithUnsupported(result, v);
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53 auto Largest = result.back().first;
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54 result.push_back({Largest + 1, Unsupported});
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55 return result;
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56 }
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57
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58 X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
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59 const X86TargetMachine &TM)
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60 : Subtarget(STI), TM(TM) {
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61
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62 setLegalizerInfo32bit();
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63 setLegalizerInfo64bit();
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64 setLegalizerInfoSSE1();
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65 setLegalizerInfoSSE2();
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66 setLegalizerInfoSSE41();
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67 setLegalizerInfoAVX();
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68 setLegalizerInfoAVX2();
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69 setLegalizerInfoAVX512();
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70 setLegalizerInfoAVX512DQ();
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71 setLegalizerInfoAVX512BW();
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72
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73 setLegalizeScalarToDifferentSizeStrategy(G_PHI, 0, widen_1);
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74 for (unsigned BinOp : {G_SUB, G_MUL, G_AND, G_OR, G_XOR})
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75 setLegalizeScalarToDifferentSizeStrategy(BinOp, 0, widen_1);
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76 for (unsigned MemOp : {G_LOAD, G_STORE})
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77 setLegalizeScalarToDifferentSizeStrategy(MemOp, 0,
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78 narrowToSmallerAndWidenToSmallest);
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79 setLegalizeScalarToDifferentSizeStrategy(
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80 G_GEP, 1, widenToLargerTypesUnsupportedOtherwise);
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81 setLegalizeScalarToDifferentSizeStrategy(
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82 G_CONSTANT, 0, widenToLargerTypesAndNarrowToLargest);
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83
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84 computeTables();
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85 }
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86
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87 void X86LegalizerInfo::setLegalizerInfo32bit() {
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88
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89 const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8);
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90 const LLT s1 = LLT::scalar(1);
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91 const LLT s8 = LLT::scalar(8);
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92 const LLT s16 = LLT::scalar(16);
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93 const LLT s32 = LLT::scalar(32);
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94 const LLT s64 = LLT::scalar(64);
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95 const LLT s128 = LLT::scalar(128);
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96
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97 for (auto Ty : {p0, s1, s8, s16, s32})
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98 setAction({G_IMPLICIT_DEF, Ty}, Legal);
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99
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100 for (auto Ty : {s8, s16, s32, p0})
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101 setAction({G_PHI, Ty}, Legal);
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102
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103 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
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104 for (auto Ty : {s8, s16, s32})
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105 setAction({BinOp, Ty}, Legal);
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106
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107 for (unsigned Op : {G_UADDE}) {
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108 setAction({Op, s32}, Legal);
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109 setAction({Op, 1, s1}, Legal);
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110 }
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111
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112 for (unsigned MemOp : {G_LOAD, G_STORE}) {
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113 for (auto Ty : {s8, s16, s32, p0})
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114 setAction({MemOp, Ty}, Legal);
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115
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116 // And everything's fine in addrspace 0.
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117 setAction({MemOp, 1, p0}, Legal);
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118 }
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119
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120 // Pointer-handling
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121 setAction({G_FRAME_INDEX, p0}, Legal);
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122 setAction({G_GLOBAL_VALUE, p0}, Legal);
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123
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124 setAction({G_GEP, p0}, Legal);
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125 setAction({G_GEP, 1, s32}, Legal);
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126
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127 // Control-flow
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128 setAction({G_BRCOND, s1}, Legal);
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129
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130 // Constants
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131 for (auto Ty : {s8, s16, s32, p0})
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132 setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
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133
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134 // Extensions
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135 for (auto Ty : {s8, s16, s32}) {
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136 setAction({G_ZEXT, Ty}, Legal);
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137 setAction({G_SEXT, Ty}, Legal);
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138 setAction({G_ANYEXT, Ty}, Legal);
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139 }
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134
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140 setAction({G_ANYEXT, s128}, Legal);
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141
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142 // Comparison
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143 setAction({G_ICMP, s1}, Legal);
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144
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145 for (auto Ty : {s8, s16, s32, p0})
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146 setAction({G_ICMP, 1, Ty}, Legal);
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134
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147
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148 // Merge/Unmerge
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149 for (const auto &Ty : {s16, s32, s64}) {
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150 setAction({G_MERGE_VALUES, Ty}, Legal);
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151 setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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152 }
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153 for (const auto &Ty : {s8, s16, s32}) {
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154 setAction({G_MERGE_VALUES, 1, Ty}, Legal);
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155 setAction({G_UNMERGE_VALUES, Ty}, Legal);
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156 }
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157 }
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158
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159 void X86LegalizerInfo::setLegalizerInfo64bit() {
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160
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161 if (!Subtarget.is64Bit())
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162 return;
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163
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164 const LLT s64 = LLT::scalar(64);
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165 const LLT s128 = LLT::scalar(128);
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166
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167 setAction({G_IMPLICIT_DEF, s64}, Legal);
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168 // Need to have that, as tryFoldImplicitDef will create this pattern:
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169 // s128 = EXTEND (G_IMPLICIT_DEF s32/s64) -> s128 = G_IMPLICIT_DEF
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170 setAction({G_IMPLICIT_DEF, s128}, Legal);
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171
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172 setAction({G_PHI, s64}, Legal);
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173
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174 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
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175 setAction({BinOp, s64}, Legal);
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176
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177 for (unsigned MemOp : {G_LOAD, G_STORE})
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178 setAction({MemOp, s64}, Legal);
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179
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180 // Pointer-handling
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181 setAction({G_GEP, 1, s64}, Legal);
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182
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183 // Constants
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184 setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
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185
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186 // Extensions
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187 for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
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188 setAction({extOp, s64}, Legal);
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189 }
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190
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191 // Comparison
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192 setAction({G_ICMP, 1, s64}, Legal);
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134
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193
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194 // Merge/Unmerge
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195 setAction({G_MERGE_VALUES, s128}, Legal);
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196 setAction({G_UNMERGE_VALUES, 1, s128}, Legal);
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197 setAction({G_MERGE_VALUES, 1, s128}, Legal);
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198 setAction({G_UNMERGE_VALUES, s128}, Legal);
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121
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199 }
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200
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201 void X86LegalizerInfo::setLegalizerInfoSSE1() {
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202 if (!Subtarget.hasSSE1())
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203 return;
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204
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205 const LLT s32 = LLT::scalar(32);
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206 const LLT s64 = LLT::scalar(64);
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207 const LLT v4s32 = LLT::vector(4, 32);
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208 const LLT v2s64 = LLT::vector(2, 64);
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209
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210 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
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211 for (auto Ty : {s32, v4s32})
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212 setAction({BinOp, Ty}, Legal);
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213
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214 for (unsigned MemOp : {G_LOAD, G_STORE})
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215 for (auto Ty : {v4s32, v2s64})
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216 setAction({MemOp, Ty}, Legal);
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217
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218 // Constants
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219 setAction({TargetOpcode::G_FCONSTANT, s32}, Legal);
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134
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220
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221 // Merge/Unmerge
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222 for (const auto &Ty : {v4s32, v2s64}) {
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223 setAction({G_MERGE_VALUES, Ty}, Legal);
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224 setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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225 }
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226 setAction({G_MERGE_VALUES, 1, s64}, Legal);
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227 setAction({G_UNMERGE_VALUES, s64}, Legal);
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121
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228 }
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229
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230 void X86LegalizerInfo::setLegalizerInfoSSE2() {
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231 if (!Subtarget.hasSSE2())
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232 return;
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233
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234 const LLT s32 = LLT::scalar(32);
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235 const LLT s64 = LLT::scalar(64);
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236 const LLT v16s8 = LLT::vector(16, 8);
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237 const LLT v8s16 = LLT::vector(8, 16);
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238 const LLT v4s32 = LLT::vector(4, 32);
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239 const LLT v2s64 = LLT::vector(2, 64);
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240
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241 const LLT v32s8 = LLT::vector(32, 8);
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242 const LLT v16s16 = LLT::vector(16, 16);
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243 const LLT v8s32 = LLT::vector(8, 32);
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244 const LLT v4s64 = LLT::vector(4, 64);
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245
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246 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
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247 for (auto Ty : {s64, v2s64})
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248 setAction({BinOp, Ty}, Legal);
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249
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250 for (unsigned BinOp : {G_ADD, G_SUB})
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251 for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
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252 setAction({BinOp, Ty}, Legal);
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253
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254 setAction({G_MUL, v8s16}, Legal);
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255
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256 setAction({G_FPEXT, s64}, Legal);
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257 setAction({G_FPEXT, 1, s32}, Legal);
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258
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259 // Constants
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260 setAction({TargetOpcode::G_FCONSTANT, s64}, Legal);
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134
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261
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262 // Merge/Unmerge
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263 for (const auto &Ty :
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264 {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
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265 setAction({G_MERGE_VALUES, Ty}, Legal);
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266 setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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267 }
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268 for (const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) {
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269 setAction({G_MERGE_VALUES, 1, Ty}, Legal);
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270 setAction({G_UNMERGE_VALUES, Ty}, Legal);
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271 }
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121
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272 }
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273
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274 void X86LegalizerInfo::setLegalizerInfoSSE41() {
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275 if (!Subtarget.hasSSE41())
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276 return;
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277
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278 const LLT v4s32 = LLT::vector(4, 32);
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279
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280 setAction({G_MUL, v4s32}, Legal);
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281 }
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282
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283 void X86LegalizerInfo::setLegalizerInfoAVX() {
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284 if (!Subtarget.hasAVX())
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285 return;
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286
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287 const LLT v16s8 = LLT::vector(16, 8);
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288 const LLT v8s16 = LLT::vector(8, 16);
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289 const LLT v4s32 = LLT::vector(4, 32);
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290 const LLT v2s64 = LLT::vector(2, 64);
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291
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292 const LLT v32s8 = LLT::vector(32, 8);
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134
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293 const LLT v64s8 = LLT::vector(64, 8);
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121
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294 const LLT v16s16 = LLT::vector(16, 16);
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134
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295 const LLT v32s16 = LLT::vector(32, 16);
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121
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296 const LLT v8s32 = LLT::vector(8, 32);
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134
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297 const LLT v16s32 = LLT::vector(16, 32);
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121
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298 const LLT v4s64 = LLT::vector(4, 64);
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134
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299 const LLT v8s64 = LLT::vector(8, 64);
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121
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300
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301 for (unsigned MemOp : {G_LOAD, G_STORE})
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302 for (auto Ty : {v8s32, v4s64})
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303 setAction({MemOp, Ty}, Legal);
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304
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305 for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) {
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306 setAction({G_INSERT, Ty}, Legal);
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307 setAction({G_EXTRACT, 1, Ty}, Legal);
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308 }
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309 for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) {
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310 setAction({G_INSERT, 1, Ty}, Legal);
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311 setAction({G_EXTRACT, Ty}, Legal);
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312 }
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134
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313 // Merge/Unmerge
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314 for (const auto &Ty :
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315 {v32s8, v64s8, v16s16, v32s16, v8s32, v16s32, v4s64, v8s64}) {
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316 setAction({G_MERGE_VALUES, Ty}, Legal);
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317 setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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318 }
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319 for (const auto &Ty :
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320 {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
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321 setAction({G_MERGE_VALUES, 1, Ty}, Legal);
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322 setAction({G_UNMERGE_VALUES, Ty}, Legal);
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323 }
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121
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324 }
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325
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326 void X86LegalizerInfo::setLegalizerInfoAVX2() {
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327 if (!Subtarget.hasAVX2())
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328 return;
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329
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330 const LLT v32s8 = LLT::vector(32, 8);
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331 const LLT v16s16 = LLT::vector(16, 16);
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332 const LLT v8s32 = LLT::vector(8, 32);
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333 const LLT v4s64 = LLT::vector(4, 64);
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334
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134
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335 const LLT v64s8 = LLT::vector(64, 8);
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336 const LLT v32s16 = LLT::vector(32, 16);
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337 const LLT v16s32 = LLT::vector(16, 32);
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338 const LLT v8s64 = LLT::vector(8, 64);
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339
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121
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340 for (unsigned BinOp : {G_ADD, G_SUB})
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341 for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
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342 setAction({BinOp, Ty}, Legal);
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343
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344 for (auto Ty : {v16s16, v8s32})
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345 setAction({G_MUL, Ty}, Legal);
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134
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346
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347 // Merge/Unmerge
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348 for (const auto &Ty : {v64s8, v32s16, v16s32, v8s64}) {
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349 setAction({G_MERGE_VALUES, Ty}, Legal);
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350 setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
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351 }
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352 for (const auto &Ty : {v32s8, v16s16, v8s32, v4s64}) {
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353 setAction({G_MERGE_VALUES, 1, Ty}, Legal);
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354 setAction({G_UNMERGE_VALUES, Ty}, Legal);
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355 }
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121
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356 }
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357
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358 void X86LegalizerInfo::setLegalizerInfoAVX512() {
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359 if (!Subtarget.hasAVX512())
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360 return;
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361
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362 const LLT v16s8 = LLT::vector(16, 8);
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363 const LLT v8s16 = LLT::vector(8, 16);
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364 const LLT v4s32 = LLT::vector(4, 32);
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365 const LLT v2s64 = LLT::vector(2, 64);
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366
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367 const LLT v32s8 = LLT::vector(32, 8);
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368 const LLT v16s16 = LLT::vector(16, 16);
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369 const LLT v8s32 = LLT::vector(8, 32);
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370 const LLT v4s64 = LLT::vector(4, 64);
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371
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372 const LLT v64s8 = LLT::vector(64, 8);
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373 const LLT v32s16 = LLT::vector(32, 16);
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374 const LLT v16s32 = LLT::vector(16, 32);
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375 const LLT v8s64 = LLT::vector(8, 64);
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376
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377 for (unsigned BinOp : {G_ADD, G_SUB})
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378 for (auto Ty : {v16s32, v8s64})
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379 setAction({BinOp, Ty}, Legal);
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380
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381 setAction({G_MUL, v16s32}, Legal);
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382
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383 for (unsigned MemOp : {G_LOAD, G_STORE})
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384 for (auto Ty : {v16s32, v8s64})
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385 setAction({MemOp, Ty}, Legal);
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386
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387 for (auto Ty : {v64s8, v32s16, v16s32, v8s64}) {
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388 setAction({G_INSERT, Ty}, Legal);
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389 setAction({G_EXTRACT, 1, Ty}, Legal);
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390 }
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391 for (auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64}) {
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392 setAction({G_INSERT, 1, Ty}, Legal);
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393 setAction({G_EXTRACT, Ty}, Legal);
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394 }
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395
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396 /************ VLX *******************/
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397 if (!Subtarget.hasVLX())
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398 return;
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399
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400 for (auto Ty : {v4s32, v8s32})
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401 setAction({G_MUL, Ty}, Legal);
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402 }
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403
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404 void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
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405 if (!(Subtarget.hasAVX512() && Subtarget.hasDQI()))
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406 return;
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407
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408 const LLT v8s64 = LLT::vector(8, 64);
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409
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410 setAction({G_MUL, v8s64}, Legal);
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411
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412 /************ VLX *******************/
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413 if (!Subtarget.hasVLX())
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414 return;
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415
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416 const LLT v2s64 = LLT::vector(2, 64);
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417 const LLT v4s64 = LLT::vector(4, 64);
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418
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419 for (auto Ty : {v2s64, v4s64})
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420 setAction({G_MUL, Ty}, Legal);
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421 }
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422
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423 void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
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424 if (!(Subtarget.hasAVX512() && Subtarget.hasBWI()))
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425 return;
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426
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427 const LLT v64s8 = LLT::vector(64, 8);
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428 const LLT v32s16 = LLT::vector(32, 16);
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429
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430 for (unsigned BinOp : {G_ADD, G_SUB})
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431 for (auto Ty : {v64s8, v32s16})
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432 setAction({BinOp, Ty}, Legal);
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433
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434 setAction({G_MUL, v32s16}, Legal);
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435
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436 /************ VLX *******************/
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437 if (!Subtarget.hasVLX())
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438 return;
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439
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440 const LLT v8s16 = LLT::vector(8, 16);
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441 const LLT v16s16 = LLT::vector(16, 16);
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442
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443 for (auto Ty : {v8s16, v16s16})
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444 setAction({G_MUL, Ty}, Legal);
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445 }
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