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annotate lib/Target/Mips/MipsTargetMachine.cpp @ 33:e4204d083e25 LLVM3.5

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LLVM 3.5
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 14:32:10 +0900
parents 95c75e76d11b
children 54457678186b
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1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // Implements the info about Mips target spec.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "MipsTargetMachine.h"
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15 #include "Mips.h"
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16 #include "MipsFrameLowering.h"
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17 #include "MipsInstrInfo.h"
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18 #include "MipsModuleISelDAGToDAG.h"
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19 #include "MipsOs16.h"
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20 #include "MipsSEFrameLowering.h"
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21 #include "MipsSEInstrInfo.h"
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22 #include "MipsSEISelLowering.h"
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23 #include "MipsSEISelDAGToDAG.h"
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24 #include "Mips16FrameLowering.h"
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25 #include "Mips16HardFloat.h"
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26 #include "Mips16InstrInfo.h"
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27 #include "Mips16ISelDAGToDAG.h"
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28 #include "Mips16ISelLowering.h"
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29 #include "llvm/Analysis/TargetTransformInfo.h"
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30 #include "llvm/CodeGen/Passes.h"
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31 #include "llvm/PassManager.h"
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32 #include "llvm/Support/Debug.h"
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33 #include "llvm/Support/raw_ostream.h"
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34 #include "llvm/Support/TargetRegistry.h"
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35 #include "llvm/Transforms/Scalar.h"
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36 using namespace llvm;
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37
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38
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39
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40 extern "C" void LLVMInitializeMipsTarget() {
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41 // Register the target.
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42 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
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43 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
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44 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
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45 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
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46 }
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47
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48 static std::string computeDataLayout(const MipsSubtarget &ST) {
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49 std::string Ret = "";
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50
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51 // There are both little and big endian mips.
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52 if (ST.isLittle())
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53 Ret += "e";
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54 else
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55 Ret += "E";
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56
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57 // Pointers are 64 or 32 bit depending on the ABI.
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58 if (ST.isABI_N64())
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59 Ret += "-p:64:64:64";
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60 else
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61 Ret += "-p:32:32:32";
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62
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63 // 8 and 16 bit integers only need no have natural alignment, but try to
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64 // align them to 32 bits. 64 bit integers have natural alignment.
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65 Ret += "-i8:8:32-i16:16:32-i64:64:64";
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66
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67 // 32 bit registers are always available and the stack is at least 64 bit
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68 // aligned. On N64 64 bit registers are also available and the stack is
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69 // 128 bit aligned.
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70 if (ST.isABI_N64())
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71 Ret += "-n32:64-S128";
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72 else
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73 Ret += "-n32-S64";
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74
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75 return Ret;
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76 }
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77
0
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78 // On function prologue, the stack is created by decrementing
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79 // its pointer. Once decremented, all references are done with positive
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80 // offset from the stack/frame pointer, using StackGrowsUp enables
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81 // an easier handling.
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82 // Using CodeModel::Large enables different CALL behavior.
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83 MipsTargetMachine::
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84 MipsTargetMachine(const Target &T, StringRef TT,
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85 StringRef CPU, StringRef FS, const TargetOptions &Options,
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86 Reloc::Model RM, CodeModel::Model CM,
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87 CodeGenOpt::Level OL,
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88 bool isLittle)
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89 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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90 Subtarget(TT, CPU, FS, isLittle, RM, this),
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91 DL(computeDataLayout(Subtarget)),
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92 InstrInfo(MipsInstrInfo::create(*this)),
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93 FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
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94 TLInfo(MipsTargetLowering::create(*this)), TSInfo(*this),
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95 InstrItins(Subtarget.getInstrItineraryData()), JITInfo() {
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96 initAsmInfo();
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97 }
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98
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99
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100 void MipsTargetMachine::setHelperClassesMips16() {
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101 InstrInfoSE.swap(InstrInfo);
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102 FrameLoweringSE.swap(FrameLowering);
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103 TLInfoSE.swap(TLInfo);
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104 if (!InstrInfo16) {
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105 InstrInfo.reset(MipsInstrInfo::create(*this));
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106 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
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107 TLInfo.reset(MipsTargetLowering::create(*this));
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108 } else {
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109 InstrInfo16.swap(InstrInfo);
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110 FrameLowering16.swap(FrameLowering);
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111 TLInfo16.swap(TLInfo);
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112 }
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113 assert(TLInfo && "null target lowering 16");
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114 assert(InstrInfo && "null instr info 16");
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115 assert(FrameLowering && "null frame lowering 16");
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116 }
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117
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118 void MipsTargetMachine::setHelperClassesMipsSE() {
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119 InstrInfo16.swap(InstrInfo);
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120 FrameLowering16.swap(FrameLowering);
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121 TLInfo16.swap(TLInfo);
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122 if (!InstrInfoSE) {
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123 InstrInfo.reset(MipsInstrInfo::create(*this));
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124 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
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125 TLInfo.reset(MipsTargetLowering::create(*this));
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126 } else {
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127 InstrInfoSE.swap(InstrInfo);
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128 FrameLoweringSE.swap(FrameLowering);
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129 TLInfoSE.swap(TLInfo);
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130 }
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131 assert(TLInfo && "null target lowering in SE");
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132 assert(InstrInfo && "null instr info SE");
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133 assert(FrameLowering && "null frame lowering SE");
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134 }
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135 void MipsebTargetMachine::anchor() { }
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136
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137 MipsebTargetMachine::
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138 MipsebTargetMachine(const Target &T, StringRef TT,
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139 StringRef CPU, StringRef FS, const TargetOptions &Options,
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140 Reloc::Model RM, CodeModel::Model CM,
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141 CodeGenOpt::Level OL)
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142 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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143
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144 void MipselTargetMachine::anchor() { }
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145
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146 MipselTargetMachine::
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147 MipselTargetMachine(const Target &T, StringRef TT,
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148 StringRef CPU, StringRef FS, const TargetOptions &Options,
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149 Reloc::Model RM, CodeModel::Model CM,
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150 CodeGenOpt::Level OL)
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151 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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152
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153 namespace {
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154 /// Mips Code Generator Pass Configuration Options.
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155 class MipsPassConfig : public TargetPassConfig {
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156 public:
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157 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
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158 : TargetPassConfig(TM, PM) {
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159 // The current implementation of long branch pass requires a scratch
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160 // register ($at) to be available before branch instructions. Tail merging
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161 // can break this requirement, so disable it when long branch pass is
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162 // enabled.
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163 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
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164 }
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165
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166 MipsTargetMachine &getMipsTargetMachine() const {
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167 return getTM<MipsTargetMachine>();
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168 }
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169
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170 const MipsSubtarget &getMipsSubtarget() const {
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171 return *getMipsTargetMachine().getSubtargetImpl();
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172 }
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173
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174 virtual void addIRPasses();
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175 virtual bool addInstSelector();
33
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176 virtual void addMachineSSAOptimization();
0
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177 virtual bool addPreEmitPass();
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178 };
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179 } // namespace
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180
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181 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
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182 return new MipsPassConfig(this, PM);
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183 }
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184
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185 void MipsPassConfig::addIRPasses() {
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186 TargetPassConfig::addIRPasses();
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187 if (getMipsSubtarget().os16())
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188 addPass(createMipsOs16(getMipsTargetMachine()));
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189 if (getMipsSubtarget().inMips16HardFloat())
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diff changeset
190 addPass(createMips16HardFloat(getMipsTargetMachine()));
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diff changeset
191 addPass(createPartiallyInlineLibCallsPass());
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192 }
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193 // Install an instruction selector pass using
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diff changeset
194 // the ISelDag to gen Mips code.
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diff changeset
195 bool MipsPassConfig::addInstSelector() {
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diff changeset
196 if (getMipsSubtarget().allowMixed16_32()) {
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diff changeset
197 addPass(createMipsModuleISelDag(getMipsTargetMachine()));
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diff changeset
198 addPass(createMips16ISelDag(getMipsTargetMachine()));
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diff changeset
199 addPass(createMipsSEISelDag(getMipsTargetMachine()));
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200 } else {
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201 addPass(createMipsISelDag(getMipsTargetMachine()));
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202 }
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203 return false;
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204 }
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205
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diff changeset
206 void MipsPassConfig::addMachineSSAOptimization() {
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207 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
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diff changeset
208 TargetPassConfig::addMachineSSAOptimization();
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209 }
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diff changeset
210
0
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diff changeset
211 void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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diff changeset
212 if (Subtarget.allowMixed16_32()) {
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diff changeset
213 DEBUG(errs() << "No ");
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diff changeset
214 //FIXME: The Basic Target Transform Info
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diff changeset
215 // pass needs to become a function pass instead of
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diff changeset
216 // being an immutable pass and then this method as it exists now
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diff changeset
217 // would be unnecessary.
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diff changeset
218 PM.add(createNoTargetTransformInfoPass());
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diff changeset
219 } else
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diff changeset
220 LLVMTargetMachine::addAnalysisPasses(PM);
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diff changeset
221 DEBUG(errs() << "Target Transform Info Pass Added\n");
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222 }
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diff changeset
223
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diff changeset
224 // Implemented by targets that want to run passes immediately before
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diff changeset
225 // machine code is emitted. return true if -print-machineinstrs should
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parents:
diff changeset
226 // print out the code after the passes.
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diff changeset
227 bool MipsPassConfig::addPreEmitPass() {
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diff changeset
228 MipsTargetMachine &TM = getMipsTargetMachine();
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diff changeset
229 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
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diff changeset
230 addPass(createMipsDelaySlotFillerPass(TM));
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parents:
diff changeset
231
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diff changeset
232 if (Subtarget.enableLongBranchPass())
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diff changeset
233 addPass(createMipsLongBranchPass(TM));
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parents:
diff changeset
234 if (Subtarget.inMips16Mode() ||
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diff changeset
235 Subtarget.allowMixed16_32())
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diff changeset
236 addPass(createMipsConstantIslandPass(TM));
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diff changeset
237
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diff changeset
238 return true;
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parents:
diff changeset
239 }
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parents:
diff changeset
240
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diff changeset
241 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 JITCodeEmitter &JCE) {
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parents:
diff changeset
243 // Machine code emitter pass for Mips.
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parents:
diff changeset
244 PM.add(createMipsJITCodeEmitterPass(*this, JCE));
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diff changeset
245 return false;
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diff changeset
246 }