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annotate llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll @ 206:f17a3b42b08b

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Added tag before-12 for changeset b7591485f4cd
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 07 Jun 2021 21:25:57 +0900
parents 1d019706d866
children c4bab56944e8
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150
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1 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX9 %s
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2 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX10 %s
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3
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4 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_1:
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5 ; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel:[0,1] op_sel_hi:[1,0]{{$}}
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6 define amdgpu_kernel void @test_pk_max_f16_literal_0_1(<2 x half> addrspace(1)* nocapture %arg) {
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7 bb:
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8 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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9 %tmp1 = zext i32 %tmp to i64
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10 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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11 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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12 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH3C00>)
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13 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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14 ret void
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15 }
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16
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17 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_0:
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18 ; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0{{$}}
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19 define amdgpu_kernel void @test_pk_max_f16_literal_1_0(<2 x half> addrspace(1)* nocapture %arg) {
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20 bb:
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21 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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22 %tmp1 = zext i32 %tmp to i64
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23 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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24 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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25 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH0000>)
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26 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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27 ret void
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28 }
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29
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30 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_1:
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31 ; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel_hi:[1,0]{{$}}
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32 define amdgpu_kernel void @test_pk_max_f16_literal_1_1(<2 x half> addrspace(1)* nocapture %arg) {
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33 bb:
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34 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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35 %tmp1 = zext i32 %tmp to i64
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36 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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37 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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38 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH3C00>)
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39 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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40 ret void
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41 }
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42
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43 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_m1:
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44 ; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0 op_sel:[0,1] op_sel_hi:[1,0]{{$}}
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45 define amdgpu_kernel void @test_pk_max_f16_literal_0_m1(<2 x half> addrspace(1)* nocapture %arg) {
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46 bb:
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47 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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48 %tmp1 = zext i32 %tmp to i64
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49 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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50 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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51 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xHBC00>)
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52 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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53 ret void
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54 }
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55
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56 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_0:
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57 ; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0{{$}}
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58 define amdgpu_kernel void @test_pk_max_f16_literal_m1_0(<2 x half> addrspace(1)* nocapture %arg) {
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59 bb:
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60 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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61 %tmp1 = zext i32 %tmp to i64
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62 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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63 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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64 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xH0000>)
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65 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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66 ret void
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67 }
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68
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69 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_m1:
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70 ; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0 op_sel_hi:[1,0]{{$}}
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71 define amdgpu_kernel void @test_pk_max_f16_literal_m1_m1(<2 x half> addrspace(1)* nocapture %arg) {
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72 bb:
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73 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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74 %tmp1 = zext i32 %tmp to i64
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75 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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76 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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77 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xHBC00>)
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78 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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79 ret void
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80 }
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81
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82 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_0:
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83 ; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 0{{$}}
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84 define amdgpu_kernel void @test_pk_max_f16_literal_0_0(<2 x half> addrspace(1)* nocapture %arg) {
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85 bb:
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86 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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87 %tmp1 = zext i32 %tmp to i64
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88 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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89 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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90 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH0000>)
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91 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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92 ret void
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93 }
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94
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95 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_41c8:
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96 ; GFX9: s_mov_b32 [[C:s[0-9]+]], 0x41c80000
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97 ; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, [[C]]{{$}}
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98 ; GFX10: v_pk_max_f16 v{{[0-9]+}}, 0x41c8, v{{[0-9]+}} op_sel:[1,0] op_sel_hi:[0,1]{{$}}
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99 define amdgpu_kernel void @test_pk_max_f16_literal_0_41c8(<2 x half> addrspace(1)* nocapture %arg) {
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100 bb:
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101 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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102 %tmp1 = zext i32 %tmp to i64
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103 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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104 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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105 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH41C8>)
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106 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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107 ret void
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108 }
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109
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110 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_41c8_0:
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111 ; GFX9: s_movk_i32 [[C:s[0-9]+]], 0x41c8
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112 ; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, [[C]]{{$}}
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113 ; GFX10: v_pk_max_f16 v{{[0-9]+}}, 0x41c8, v{{[0-9]+}}{{$}}
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114 define amdgpu_kernel void @test_pk_max_f16_literal_41c8_0(<2 x half> addrspace(1)* nocapture %arg) {
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115 bb:
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116 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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117 %tmp1 = zext i32 %tmp to i64
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118 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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119 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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120 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH41C8, half 0xH0>)
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121 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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122 ret void
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123 }
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124
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125 ; GCN-LABEL: {{^}}test_pk_max_f16_literal_42ca_41c8:
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126 ; GFX9: s_mov_b32 [[C:s[0-9]+]], 0x41c842ca
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127 ; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, [[C]]{{$}}
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128 ; GFX10: v_pk_max_f16 v{{[0-9]+}}, 0x41c842ca, v{{[0-9]+}}{{$}}
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129 define amdgpu_kernel void @test_pk_max_f16_literal_42ca_41c8(<2 x half> addrspace(1)* nocapture %arg) {
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130 bb:
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131 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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132 %tmp1 = zext i32 %tmp to i64
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133 %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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134 %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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135 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH42CA, half 0xH41C8>)
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136 store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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137 ret void
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138 }
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139
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140 declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
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141 declare i32 @llvm.amdgcn.workitem.id.x()