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annotate lib/Target/ARM/ARMBaseInstrInfo.h @ 131:f476a9ba4795

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http://llvm.org/svn/llvm-project/compiler-rt/trunk compiler-rt
author mir3636
date Fri, 16 Feb 2018 21:02:11 +0900
parents 803732b1fca8
children 3a76565eade5
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1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
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15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
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16
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17 #include "MCTargetDesc/ARMBaseInfo.h"
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18 #include "llvm/ADT/DenseMap.h"
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19 #include "llvm/ADT/SmallSet.h"
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20 #include "llvm/CodeGen/MachineBasicBlock.h"
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21 #include "llvm/CodeGen/MachineInstr.h"
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22 #include "llvm/CodeGen/MachineInstrBuilder.h"
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23 #include "llvm/CodeGen/MachineOperand.h"
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24 #include "llvm/Target/TargetInstrInfo.h"
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25 #include <array>
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26 #include <cstdint>
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27
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28 #define GET_INSTRINFO_HEADER
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29 #include "ARMGenInstrInfo.inc"
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30
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31 namespace llvm {
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32
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33 class ARMBaseRegisterInfo;
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34 class ARMSubtarget;
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35
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36 class ARMBaseInstrInfo : public ARMGenInstrInfo {
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37 const ARMSubtarget &Subtarget;
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38
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39 protected:
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40 // Can be only subclassed.
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41 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
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42
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43 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
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44 unsigned LoadImmOpc, unsigned LoadOpc) const;
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45
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46 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
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47 /// and \p DefIdx.
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48 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
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49 /// the list is modeled as <Reg:SubReg, SubIdx>.
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50 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
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51 /// two elements:
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52 /// - vreg1:sub1, sub0
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53 /// - vreg2<:0>, sub1
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54 ///
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55 /// \returns true if it is possible to build such an input sequence
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56 /// with the pair \p MI, \p DefIdx. False otherwise.
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57 ///
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58 /// \pre MI.isRegSequenceLike().
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59 bool getRegSequenceLikeInputs(
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60 const MachineInstr &MI, unsigned DefIdx,
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61 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
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62
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63 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
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64 /// and \p DefIdx.
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65 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
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66 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
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67 /// - vreg1:sub1, sub0
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68 ///
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69 /// \returns true if it is possible to build such an input sequence
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70 /// with the pair \p MI, \p DefIdx. False otherwise.
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71 ///
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72 /// \pre MI.isExtractSubregLike().
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73 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
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74 RegSubRegPairAndIdx &InputReg) const override;
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75
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76 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
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77 /// and \p DefIdx.
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78 /// \p [out] BaseReg and \p [out] InsertedReg contain
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79 /// the equivalent inputs of INSERT_SUBREG.
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80 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
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81 /// - BaseReg: vreg0:sub0
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82 /// - InsertedReg: vreg1:sub1, sub3
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83 ///
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84 /// \returns true if it is possible to build such an input sequence
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85 /// with the pair \p MI, \p DefIdx. False otherwise.
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86 ///
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87 /// \pre MI.isInsertSubregLike().
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88 bool
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89 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
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90 RegSubRegPair &BaseReg,
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91 RegSubRegPairAndIdx &InsertedReg) const override;
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92
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93 /// Commutes the operands in the given instruction.
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94 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
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95 ///
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96 /// Do not call this method for a non-commutable instruction or for
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97 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
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98 /// Even though the instruction is commutable, the method may still
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99 /// fail to commute the operands, null pointer is returned in such cases.
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100 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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101 unsigned OpIdx1,
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102 unsigned OpIdx2) const override;
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103
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104 public:
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105 // Return whether the target has an explicit NOP encoding.
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106 bool hasNOP() const;
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107
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108 // Return the non-pre/post incrementing version of 'Opc'. Return 0
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109 // if there is not such an opcode.
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110 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
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111
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112 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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113 MachineInstr &MI,
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114 LiveVariables *LV) const override;
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115
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116 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
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117 const ARMSubtarget &getSubtarget() const { return Subtarget; }
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118
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119 ScheduleHazardRecognizer *
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120 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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121 const ScheduleDAG *DAG) const override;
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122
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123 ScheduleHazardRecognizer *
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124 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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125 const ScheduleDAG *DAG) const override;
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126
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127 // Branch analysis.
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128 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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129 MachineBasicBlock *&FBB,
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130 SmallVectorImpl<MachineOperand> &Cond,
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131 bool AllowModify = false) const override;
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132 unsigned removeBranch(MachineBasicBlock &MBB,
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133 int *BytesRemoved = nullptr) const override;
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134 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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135 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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136 const DebugLoc &DL,
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137 int *BytesAdded = nullptr) const override;
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138
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139 bool
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140 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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141
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142 // Predication support.
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143 bool isPredicated(const MachineInstr &MI) const override;
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144
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145 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
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146 int PIdx = MI.findFirstPredOperandIdx();
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147 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
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148 : ARMCC::AL;
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149 }
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150
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151 bool PredicateInstruction(MachineInstr &MI,
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152 ArrayRef<MachineOperand> Pred) const override;
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153
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154 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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155 ArrayRef<MachineOperand> Pred2) const override;
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156
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157 bool DefinesPredicate(MachineInstr &MI,
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158 std::vector<MachineOperand> &Pred) const override;
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159
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160 bool isPredicable(const MachineInstr &MI) const override;
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161
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162 // CPSR defined in instruction
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163 static bool isCPSRDefined(const MachineInstr &MI);
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164 bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
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165 bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
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166
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167 // Load, scaled register offset
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168 bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
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169 // Load, scaled register offset, not plus LSL2
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170 bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
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171 // Minus reg for ldstso addr mode
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172 bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
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173 // Scaled register offset in address mode 2
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174 bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
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175 // Load multiple, base reg in list
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176 bool isLDMBaseRegInList(const MachineInstr &MI) const;
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177 // get LDM variable defs size
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178 unsigned getLDMVariableDefsSize(const MachineInstr &MI) const;
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179
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180 /// GetInstSize - Returns the size of the specified MachineInstr.
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181 ///
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182 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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183
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184 unsigned isLoadFromStackSlot(const MachineInstr &MI,
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185 int &FrameIndex) const override;
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186 unsigned isStoreToStackSlot(const MachineInstr &MI,
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187 int &FrameIndex) const override;
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188 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
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189 int &FrameIndex) const override;
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190 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
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191 int &FrameIndex) const override;
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192
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193 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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194 unsigned SrcReg, bool KillSrc,
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195 const ARMSubtarget &Subtarget) const;
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196 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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197 unsigned DestReg, bool KillSrc,
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198 const ARMSubtarget &Subtarget) const;
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199
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200 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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201 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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202 bool KillSrc) const override;
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203
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204 void storeRegToStackSlot(MachineBasicBlock &MBB,
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205 MachineBasicBlock::iterator MBBI,
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206 unsigned SrcReg, bool isKill, int FrameIndex,
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207 const TargetRegisterClass *RC,
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208 const TargetRegisterInfo *TRI) const override;
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209
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210 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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211 MachineBasicBlock::iterator MBBI,
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212 unsigned DestReg, int FrameIndex,
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213 const TargetRegisterClass *RC,
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214 const TargetRegisterInfo *TRI) const override;
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215
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216 bool expandPostRAPseudo(MachineInstr &MI) const override;
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217
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218 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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219 unsigned DestReg, unsigned SubIdx,
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220 const MachineInstr &Orig,
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221 const TargetRegisterInfo &TRI) const override;
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222
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223 MachineInstr &
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224 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
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225 const MachineInstr &Orig) const override;
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226
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227 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
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228 unsigned SubIdx, unsigned State,
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229 const TargetRegisterInfo *TRI) const;
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230
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231 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
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232 const MachineRegisterInfo *MRI) const override;
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233
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234 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
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235 /// determine if two loads are loading from the same base address. It should
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236 /// only return true if the base pointers are the same and the only
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237 /// differences between the two addresses is the offset. It also returns the
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238 /// offsets by reference.
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239 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
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240 int64_t &Offset2) const override;
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241
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242 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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243 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
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244 /// should be scheduled togther. On some targets if two loads are loading from
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245 /// addresses in the same cache line, it's better if they are scheduled
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246 /// together. This function takes two integers that represent the load offsets
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247 /// from the common base address. It returns true if it decides it's desirable
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248 /// to schedule the two loads together. "NumLoads" is the number of loads that
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249 /// have already been scheduled after Load1.
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250 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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251 int64_t Offset1, int64_t Offset2,
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252 unsigned NumLoads) const override;
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253
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254 bool isSchedulingBoundary(const MachineInstr &MI,
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255 const MachineBasicBlock *MBB,
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256 const MachineFunction &MF) const override;
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257
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258 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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259 unsigned NumCycles, unsigned ExtraPredCycles,
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260 BranchProbability Probability) const override;
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261
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262 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
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263 unsigned ExtraT, MachineBasicBlock &FMBB,
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264 unsigned NumF, unsigned ExtraF,
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265 BranchProbability Probability) const override;
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266
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267 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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268 BranchProbability Probability) const override {
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269 return NumCycles == 1;
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270 }
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271
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272 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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273 MachineBasicBlock &FMBB) const override;
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274
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275 /// analyzeCompare - For a comparison instruction, return the source registers
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276 /// in SrcReg and SrcReg2 if having two register operands, and the value it
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277 /// compares against in CmpValue. Return true if the comparison instruction
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278 /// can be analyzed.
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279 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
77
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280 unsigned &SrcReg2, int &CmpMask,
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281 int &CmpValue) const override;
0
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282
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283 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
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284 /// that we can remove a "comparison with zero"; Remove a redundant CMP
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285 /// instruction if the flags can be updated in the same way by an earlier
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286 /// instruction such as SUB.
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287 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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288 unsigned SrcReg2, int CmpMask, int CmpValue,
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289 const MachineRegisterInfo *MRI) const override;
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290
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291 bool analyzeSelect(const MachineInstr &MI,
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292 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
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293 unsigned &FalseOp, bool &Optimizable) const override;
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294
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295 MachineInstr *optimizeSelect(MachineInstr &MI,
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296 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
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297 bool) const override;
0
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298
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299 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
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300 /// instruction, try to fold the immediate into the use instruction.
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301 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
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302 MachineRegisterInfo *MRI) const override;
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303
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304 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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305 const MachineInstr &MI) const override;
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306
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307 int getOperandLatency(const InstrItineraryData *ItinData,
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308 const MachineInstr &DefMI, unsigned DefIdx,
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309 const MachineInstr &UseMI,
77
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310 unsigned UseIdx) const override;
0
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311 int getOperandLatency(const InstrItineraryData *ItinData,
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312 SDNode *DefNode, unsigned DefIdx,
77
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313 SDNode *UseNode, unsigned UseIdx) const override;
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314
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315 /// VFP/NEON execution domains.
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316 std::pair<uint16_t, uint16_t>
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317 getExecutionDomain(const MachineInstr &MI) const override;
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318 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
0
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319
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320 unsigned
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321 getPartialRegUpdateClearance(const MachineInstr &, unsigned,
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322 const TargetRegisterInfo *) const override;
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323 void breakPartialRegDependency(MachineInstr &, unsigned,
77
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324 const TargetRegisterInfo *TRI) const override;
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325
0
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326 /// Get the number of addresses by LDM or VLDM or zero for unknown.
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327 unsigned getNumLDMAddresses(const MachineInstr &MI) const;
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328
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329 private:
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330 unsigned getInstBundleLength(const MachineInstr &MI) const;
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331
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332 int getVLDMDefCycle(const InstrItineraryData *ItinData,
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333 const MCInstrDesc &DefMCID,
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334 unsigned DefClass,
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335 unsigned DefIdx, unsigned DefAlign) const;
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336 int getLDMDefCycle(const InstrItineraryData *ItinData,
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337 const MCInstrDesc &DefMCID,
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338 unsigned DefClass,
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339 unsigned DefIdx, unsigned DefAlign) const;
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340 int getVSTMUseCycle(const InstrItineraryData *ItinData,
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341 const MCInstrDesc &UseMCID,
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342 unsigned UseClass,
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343 unsigned UseIdx, unsigned UseAlign) const;
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344 int getSTMUseCycle(const InstrItineraryData *ItinData,
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345 const MCInstrDesc &UseMCID,
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346 unsigned UseClass,
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347 unsigned UseIdx, unsigned UseAlign) const;
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348 int getOperandLatency(const InstrItineraryData *ItinData,
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349 const MCInstrDesc &DefMCID,
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350 unsigned DefIdx, unsigned DefAlign,
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351 const MCInstrDesc &UseMCID,
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352 unsigned UseIdx, unsigned UseAlign) const;
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353
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354 int getOperandLatencyImpl(const InstrItineraryData *ItinData,
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355 const MachineInstr &DefMI, unsigned DefIdx,
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356 const MCInstrDesc &DefMCID, unsigned DefAdj,
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357 const MachineOperand &DefMO, unsigned Reg,
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358 const MachineInstr &UseMI, unsigned UseIdx,
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359 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
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360
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361 unsigned getPredicationCost(const MachineInstr &MI) const override;
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362
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diff changeset
363 unsigned getInstrLatency(const InstrItineraryData *ItinData,
120
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364 const MachineInstr &MI,
77
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diff changeset
365 unsigned *PredCost = nullptr) const override;
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diff changeset
366
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367 int getInstrLatency(const InstrItineraryData *ItinData,
77
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diff changeset
368 SDNode *Node) const override;
0
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diff changeset
369
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diff changeset
370 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
0
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371 const MachineRegisterInfo *MRI,
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372 const MachineInstr &DefMI, unsigned DefIdx,
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373 const MachineInstr &UseMI,
77
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374 unsigned UseIdx) const override;
95
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diff changeset
375 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
120
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376 const MachineInstr &DefMI,
77
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diff changeset
377 unsigned DefIdx) const override;
0
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diff changeset
378
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379 /// verifyInstruction - Perform target specific instruction verification.
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380 bool verifyInstruction(const MachineInstr &MI,
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diff changeset
381 StringRef &ErrInfo) const override;
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diff changeset
382
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383 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
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diff changeset
384
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diff changeset
385 void expandMEMCPY(MachineBasicBlock::iterator) const;
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diff changeset
386
0
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diff changeset
387 private:
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388 /// Modeling special VFP / NEON fp MLA / MLS hazards.
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diff changeset
389
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diff changeset
390 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
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diff changeset
391 /// MLx table.
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diff changeset
392 DenseMap<unsigned, unsigned> MLxEntryMap;
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diff changeset
393
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diff changeset
394 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
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diff changeset
395 /// stalls when scheduled together with fp MLA / MLS opcodes.
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parents:
diff changeset
396 SmallSet<unsigned, 16> MLxHazardOpcodes;
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parents:
diff changeset
397
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diff changeset
398 public:
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diff changeset
399 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
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parents:
diff changeset
400 /// instruction.
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diff changeset
401 bool isFpMLxInstruction(unsigned Opcode) const {
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diff changeset
402 return MLxEntryMap.count(Opcode);
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diff changeset
403 }
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parents:
diff changeset
404
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parents:
diff changeset
405 /// isFpMLxInstruction - This version also returns the multiply opcode and the
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
407 /// the MLX instructions with an extra lane operand.
95c75e76d11b LLVM 3.4
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parents:
diff changeset
408 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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parents:
diff changeset
409 unsigned &AddSubOpc, bool &NegAcc,
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parents:
diff changeset
410 bool &HasLane) const;
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parents:
diff changeset
411
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
412 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 /// will cause stalls when scheduled after (within 4-cycle window) a fp
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
414 /// MLA / MLS instruction.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
415 bool canCauseFpMLxStall(unsigned Opcode) const {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
416 return MLxHazardOpcodes.count(Opcode);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
417 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
418
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
419 /// Returns true if the instruction has a shift by immediate that can be
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
420 /// executed in one cycle less.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 bool isSwiftFastImmShift(const MachineInstr *MI) const;
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
422
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
423 /// Returns predicate register associated with the given frame instruction.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
424 unsigned getFramePred(const MachineInstr &MI) const {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
425 assert(isFrameInstr(MI));
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
426 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
427 // - argument declared in the pattern:
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
428 // 0 - frame size
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
429 // 1 - arg of CALLSEQ_START/CALLSEQ_END
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
430 // 2 - predicate code (like ARMCC::AL)
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
431 // - added by predOps:
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
432 // 3 - predicate reg
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
433 return MI.getOperand(3).getReg();
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
434 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
435 };
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
436
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
437 /// Get the operands corresponding to the given \p Pred value. By default, the
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
438 /// predicate register is assumed to be 0 (no register), but you can pass in a
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
439 /// \p PredReg if that is not the case.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
440 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
441 unsigned PredReg = 0) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
442 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
443 MachineOperand::CreateReg(PredReg, false)}};
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
444 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
445
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
446 /// Get the operand corresponding to the conditional code result. By default,
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
447 /// this is 0 (no register).
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
448 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
449 return MachineOperand::CreateReg(CCReg, false);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
450 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
451
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
452 /// Get the operand corresponding to the conditional code result for Thumb1.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
453 /// This operand will always refer to CPSR and it will have the Define flag set.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
454 /// You can optionally set the Dead flag by means of \p isDead.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
455 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
456 return MachineOperand::CreateReg(ARM::CPSR,
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
457 /*Define*/ true, /*Implicit*/ false,
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
458 /*Kill*/ false, isDead);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
459 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
460
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
461 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
462 bool isUncondBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
463 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
464 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
465
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
466 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
467 bool isCondBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
468 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
469 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
470
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
471 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
472 bool isJumpTableBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
473 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
474 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
475 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
476
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
477 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
478 bool isIndirectBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
479 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
480 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
481
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
482 static inline bool isPopOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
483 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
484 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
485 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
486 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
487
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
488 static inline bool isPushOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
489 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
490 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
491 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
492
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
493 /// getInstrPredicate - If instruction is predicated, returns its predicate
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
494 /// condition, otherwise returns AL. It also returns the condition code
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
495 /// register by reference.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
496 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
497
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
498 unsigned getMatchingCondBranchOpcode(unsigned Opc);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
499
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
500 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
501 /// opcode of the SSA instruction representing the conditional MI.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
502 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
503 MachineInstr *&MI,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
504 const MachineRegisterInfo &MRI);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
505
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
506 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
507 /// the instruction is encoded with an 'S' bit is determined by the optional
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
508 /// CPSR def operand.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
509 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
510
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
511 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
512 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
513 /// code.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
514 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
515 MachineBasicBlock::iterator &MBBI,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
516 const DebugLoc &dl, unsigned DestReg,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
517 unsigned BaseReg, int NumBytes,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
518 ARMCC::CondCodes Pred, unsigned PredReg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
519 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
520
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
521 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
522 MachineBasicBlock::iterator &MBBI,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
523 const DebugLoc &dl, unsigned DestReg,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
524 unsigned BaseReg, int NumBytes,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
525 ARMCC::CondCodes Pred, unsigned PredReg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
526 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
527 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
528 MachineBasicBlock::iterator &MBBI,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
529 const DebugLoc &dl, unsigned DestReg,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
530 unsigned BaseReg, int NumBytes,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
531 const TargetInstrInfo &TII,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
532 const ARMBaseRegisterInfo &MRI,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
533 unsigned MIFlags = 0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
534
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
535 /// Tries to add registers to the reglist of a given base-updating
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
536 /// push/pop instruction to adjust the stack by an additional
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
537 /// NumBytes. This can save a few bytes per function in code-size, but
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
538 /// obviously generates more memory traffic. As such, it only takes
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
539 /// effect in functions being optimised for size.
33
e4204d083e25 LLVM 3.5
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
540 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
e4204d083e25 LLVM 3.5
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
541 MachineFunction &MF, MachineInstr *MI,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
542 unsigned NumBytes);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
543
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
544 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
545 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
546 /// offset could not be handled directly in MI, and return the left-over
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
547 /// portion by reference.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
548 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
549 unsigned FrameReg, int &Offset,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
550 const ARMBaseInstrInfo &TII);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
551
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
552 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
95c75e76d11b LLVM 3.4
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553 unsigned FrameReg, int &Offset,
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554 const ARMBaseInstrInfo &TII);
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555
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556 } // end namespace llvm
0
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557
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558 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H