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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
2 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
3 // The LLVM Compiler Infrastructure
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
4 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
5 // This file is distributed under the University of Illinois Open Source
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
6 // License. See LICENSE.TXT for details.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
7 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
8 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
9 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
10 // This file describes the Mips FPU instruction set.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
11 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
12 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
13
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
14 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
15 // Floating Point Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
16 // ------------------------
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
17 // * 64bit fp:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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18 // - 32 64-bit registers (default mode)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
19 // - 16 even 32-bit registers (32-bit compatible mode) for
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
20 // single and double access.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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21 // * 32bit fp:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
22 // - 16 even 32-bit registers - single and double (aliased)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
23 // - 32 32-bit registers (within single-only mode)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
24 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
25
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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26 // Floating Point Compare and Branch
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 SDTCisVT<1, i32>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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29 SDTCisVT<2, OtherVT>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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30 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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31 SDTCisVT<2, i32>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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32 def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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33 SDTCisSameAs<1, 3>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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34 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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35 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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36 SDTCisVT<1, i32>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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37 SDTCisSameAs<1, 2>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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38 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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39 SDTCisVT<1, f64>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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40 SDTCisVT<2, i32>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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41
|
|
121
|
42 def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>,
|
|
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43 SDTCisVT<1, i32>]>;
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|
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44
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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45 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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46 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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47 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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48 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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49 [SDNPHasChain, SDNPOptInGlue]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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50 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
51 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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52 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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53 SDT_MipsExtractElementF64>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
54
|
|
121
|
55 def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;
|
|
|
56
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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57 // Operand for printing out a condition code.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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58 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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59 def condcode : Operand<i32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
60
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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61 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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62 // Feature predicates.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
63 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
64
|
|
77
|
65 def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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66 AssemblerPredicate<"FeatureFP64Bit">;
|
|
77
|
67 def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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68 AssemblerPredicate<"!FeatureFP64Bit">;
|
|
77
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69 def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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70 AssemblerPredicate<"FeatureSingleFloat">;
|
|
77
|
71 def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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72 AssemblerPredicate<"!FeatureSingleFloat">;
|
|
95
|
73 def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">,
|
|
|
74 AssemblerPredicate<"!FeatureSoftFloat">;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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75
|
|
77
|
76 //===----------------------------------------------------------------------===//
|
|
|
77 // Mips FGR size adjectives.
|
|
|
78 // They are mutually exclusive.
|
|
|
79 //===----------------------------------------------------------------------===//
|
|
|
80
|
|
|
81 class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
|
|
|
82 class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
|
|
95
|
83 class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; }
|
|
77
|
84
|
|
|
85 //===----------------------------------------------------------------------===//
|
|
|
86
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
87 // FP immediate patterns.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
88 def fpimm0 : PatLeaf<(fpimm), [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
89 return N->isExactlyValue(+0.0);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
90 }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
91
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
92 def fpimm0neg : PatLeaf<(fpimm), [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
93 return N->isExactlyValue(-0.0);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
94 }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
95
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
96 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
97 // Instruction Class Templates
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
98 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
99 // A set of multiclasses is used to address the register usage.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
100 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
101 // S32 - single precision in 16 32bit even fp registers
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
102 // single precision in 32 32bit fp registers in SingleOnly mode
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
103 // S64 - single precision in 32 64bit fp registers (In64BitMode)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
104 // D32 - double precision in 16 32bit even fp registers
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
105 // D64 - double precision in 32 64bit fp registers (In64BitMode)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
106 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
107 // Only S32 and D32 are supported right now.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
108 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
109 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
110 SDPatternOperator OpNode= null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
111 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
112 !strconcat(opstr, "\t$fd, $fs, $ft"),
|
|
95
|
113 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
|
|
|
114 HARDFLOAT {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
115 let isCommutable = IsComm;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
116 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
117
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
118 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
119 SDPatternOperator OpNode = null_frag> {
|
|
95
|
120 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
|
|
|
121 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
|
|
121
|
122 string DecoderNamespace = "MipsFP64";
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
123 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
124 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
125
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
126 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
127 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
128 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
|
|
77
|
129 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
|
|
95
|
130 HARDFLOAT,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
131 NeverHasSideEffects;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
132
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
133 multiclass ABSS_M<string opstr, InstrItinClass Itin,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
134 SDPatternOperator OpNode= null_frag> {
|
|
77
|
135 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
|
|
95
|
136 FGR_32;
|
|
|
137 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
|
|
121
|
138 string DecoderNamespace = "MipsFP64";
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
139 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
140 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
141
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
142 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
|
|
95
|
143 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
|
|
100
|
144 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
|
|
121
|
145 let DecoderNamespace = "MipsFP64";
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
146 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
147 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
148
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
149 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
150 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
151 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
|
|
95
|
152 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
153
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
154 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
155 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
156 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
|
|
95
|
157 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
|
|
77
|
158
|
|
|
159 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
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160 InstrItinClass Itin> :
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161 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
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95
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162 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT {
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77
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163 // $fs_in is part of a white lie to work around a widespread bug in the FPU
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164 // implementation. See expandBuildPairF64 for details.
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165 let Constraints = "$fs = $fs_in";
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166 }
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167
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120
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168 class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
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169 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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170 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
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95
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171 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
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172 HARDFLOAT {
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173 let DecoderMethod = "DecodeFMem";
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174 let mayLoad = 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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175 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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176
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120
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177 class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
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178 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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179 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
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95
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180 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
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181 let DecoderMethod = "DecodeFMem";
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182 let mayStore = 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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183 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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184
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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185 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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186 SDPatternOperator OpNode = null_frag> :
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187 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
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188 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
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77
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189 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
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95
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190 FrmFR, opstr>, HARDFLOAT;
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191
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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192 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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193 SDPatternOperator OpNode = null_frag> :
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194 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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195 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
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196 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
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95
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197 Itin, FrmFR, opstr>, HARDFLOAT;
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198
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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199 class LWXC1_FT<string opstr, RegisterOperand DRC,
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200 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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201 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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202 !strconcat(opstr, "\t$fd, ${index}(${base})"),
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77
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203 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
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95
|
204 FrmFI, opstr>, HARDFLOAT {
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205 let AddedComplexity = 20;
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parents:
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206 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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207
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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208 class SWXC1_FT<string opstr, RegisterOperand DRC,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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209 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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210 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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211 !strconcat(opstr, "\t$fs, ${index}(${base})"),
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77
|
212 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
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|
95
|
213 FrmFI, opstr>, HARDFLOAT {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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214 let AddedComplexity = 20;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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215 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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216
|
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77
|
217 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
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|
121
|
218 SDPatternOperator Op = null_frag> :
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77
|
219 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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220 !strconcat(opstr, "\t$fcc, $offset"),
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77
|
221 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
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95
|
222 FrmFI, opstr>, HARDFLOAT {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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223 let isBranch = 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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224 let isTerminator = 1;
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121
|
225 let hasDelaySlot = 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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226 let Defs = [AT];
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121
|
227 let hasFCCRegOperand = 1;
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228 }
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229
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230 class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
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231 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
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|
232 !strconcat(opstr, "\t$fcc, $offset"), [], Itin,
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|
233 FrmFI, opstr>, HARDFLOAT {
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|
234 let isBranch = 1;
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|
235 let isTerminator = 1;
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236 let hasDelaySlot = 1;
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|
237 let Defs = [AT];
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|
238 let hasFCCRegOperand = 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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239 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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240
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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241 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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242 SDPatternOperator OpNode = null_frag> :
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
243 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
244 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
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|
77
|
245 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
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95
|
246 !strconcat("c.$cond.", typestr)>, HARDFLOAT {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
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247 let Defs = [FCC0];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
248 let isCodeGenOnly = 1;
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|
121
|
249 let hasFCCRegOperand = 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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250 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
251
|
|
121
|
252
|
|
|
253 // Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather
|
|
|
254 // duplicating the instruction definition for MIPS1 - MIPS3, we expand
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|
|
255 // c.cond.ft if necessary, and reject it after constructing the
|
|
|
256 // instruction if the ISA doesn't support it.
|
|
77
|
257 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
|
|
|
258 InstrItinClass itin> :
|
|
121
|
259 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft),
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|
|
260 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin,
|
|
|
261 FrmFR>, HARDFLOAT {
|
|
|
262 let isCompare = 1;
|
|
|
263 let hasFCCRegOperand = 1;
|
|
|
264 }
|
|
|
265
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
266
|
|
77
|
267 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
|
|
|
268 InstrItinClass itin> {
|
|
121
|
269 def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
|
|
|
270 C_COND_FM<fmt, 0> {
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|
|
271 let BaseOpcode = "c.f."#NAME;
|
|
|
272 let isCommutable = 1;
|
|
|
273 }
|
|
|
274 def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,
|
|
|
275 C_COND_FM<fmt, 1> {
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|
|
276 let BaseOpcode = "c.un."#NAME;
|
|
|
277 let isCommutable = 1;
|
|
|
278 }
|
|
|
279 def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,
|
|
|
280 C_COND_FM<fmt, 2> {
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|
|
281 let BaseOpcode = "c.eq."#NAME;
|
|
|
282 let isCommutable = 1;
|
|
|
283 }
|
|
|
284 def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,
|
|
|
285 C_COND_FM<fmt, 3> {
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|
|
286 let BaseOpcode = "c.ueq."#NAME;
|
|
|
287 let isCommutable = 1;
|
|
|
288 }
|
|
|
289 def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,
|
|
|
290 C_COND_FM<fmt, 4> {
|
|
|
291 let BaseOpcode = "c.olt."#NAME;
|
|
|
292 }
|
|
|
293 def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,
|
|
|
294 C_COND_FM<fmt, 5> {
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|
|
295 let BaseOpcode = "c.ult."#NAME;
|
|
|
296 }
|
|
|
297 def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,
|
|
|
298 C_COND_FM<fmt, 6> {
|
|
|
299 let BaseOpcode = "c.ole."#NAME;
|
|
|
300 }
|
|
|
301 def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,
|
|
|
302 C_COND_FM<fmt, 7> {
|
|
|
303 let BaseOpcode = "c.ule."#NAME;
|
|
|
304 }
|
|
|
305 def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,
|
|
|
306 C_COND_FM<fmt, 8> {
|
|
|
307 let BaseOpcode = "c.sf."#NAME;
|
|
|
308 let isCommutable = 1;
|
|
|
309 }
|
|
|
310 def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,
|
|
|
311 C_COND_FM<fmt, 9> {
|
|
|
312 let BaseOpcode = "c.ngle."#NAME;
|
|
|
313 }
|
|
|
314 def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,
|
|
|
315 C_COND_FM<fmt, 10> {
|
|
|
316 let BaseOpcode = "c.seq."#NAME;
|
|
|
317 let isCommutable = 1;
|
|
|
318 }
|
|
|
319 def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,
|
|
|
320 C_COND_FM<fmt, 11> {
|
|
|
321 let BaseOpcode = "c.ngl."#NAME;
|
|
|
322 }
|
|
|
323 def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,
|
|
|
324 C_COND_FM<fmt, 12> {
|
|
|
325 let BaseOpcode = "c.lt."#NAME;
|
|
|
326 }
|
|
|
327 def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,
|
|
|
328 C_COND_FM<fmt, 13> {
|
|
|
329 let BaseOpcode = "c.nge."#NAME;
|
|
|
330 }
|
|
|
331 def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,
|
|
|
332 C_COND_FM<fmt, 14> {
|
|
|
333 let BaseOpcode = "c.le."#NAME;
|
|
|
334 }
|
|
|
335 def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
|
|
|
336 C_COND_FM<fmt, 15> {
|
|
|
337 let BaseOpcode = "c.ngt."#NAME;
|
|
|
338 }
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
339 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
340
|
|
121
|
341 let AdditionalPredicates = [NotInMicroMips] in {
|
|
77
|
342 defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
343 defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
|
|
95
|
344 FGR_32;
|
|
121
|
345 let DecoderNamespace = "MipsFP64" in
|
|
77
|
346 defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
|
|
95
|
347 FGR_64;
|
|
121
|
348 }
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
349 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
350 // Floating Point Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
351 //===----------------------------------------------------------------------===//
|
|
100
|
352 def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
|
|
77
|
353 ABSS_FM<0xc, 16>, ISA_MIPS2;
|
|
100
|
354 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
|
|
95
|
355 def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
|
|
77
|
356 ABSS_FM<0xd, 16>, ISA_MIPS2;
|
|
95
|
357 def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
|
|
77
|
358 ABSS_FM<0xe, 16>, ISA_MIPS2;
|
|
95
|
359 def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
|
|
77
|
360 ABSS_FM<0xf, 16>, ISA_MIPS2;
|
|
|
361 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
362 ABSS_FM<0x24, 16>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
363
|
|
77
|
364 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
|
|
|
365 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
|
|
|
366 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
|
|
|
367 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
368
|
|
120
|
369 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
370 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
|
|
|
371 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
|
|
121
|
372 def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>,
|
|
|
373 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 {
|
|
|
374 let BaseOpcode = "RECIP_D32";
|
|
|
375 }
|
|
|
376 let DecoderNamespace = "MipsFP64" in
|
|
|
377 def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
|
|
|
378 II_RECIP_D>, ABSS_FM<0b010101, 0x11>,
|
|
|
379 INSN_MIPS4_32R2, FGR_64;
|
|
120
|
380 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
|
|
|
381 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
|
|
121
|
382 def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>,
|
|
|
383 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 {
|
|
|
384 let BaseOpcode = "RSQRT_D32";
|
|
|
385 }
|
|
|
386 let DecoderNamespace = "MipsFP64" in
|
|
|
387 def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
|
|
|
388 II_RSQRT_D>, ABSS_FM<0b010110, 0x11>,
|
|
|
389 INSN_MIPS4_32R2, FGR_64;
|
|
120
|
390 }
|
|
121
|
391 let DecoderNamespace = "MipsFP64" in {
|
|
100
|
392 let AdditionalPredicates = [NotInMicroMips] in {
|
|
77
|
393 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
|
|
|
394 ABSS_FM<0x8, 16>, FGR_64;
|
|
|
395 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
|
|
|
396 ABSS_FM<0x8, 17>, FGR_64;
|
|
|
397 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
|
|
|
398 ABSS_FM<0x9, 16>, FGR_64;
|
|
|
399 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
|
|
|
400 ABSS_FM<0x9, 17>, FGR_64;
|
|
|
401 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
|
|
|
402 ABSS_FM<0xa, 16>, FGR_64;
|
|
|
403 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
|
|
|
404 ABSS_FM<0xa, 17>, FGR_64;
|
|
|
405 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
|
|
|
406 ABSS_FM<0xb, 16>, FGR_64;
|
|
|
407 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
|
|
|
408 ABSS_FM<0xb, 17>, FGR_64;
|
|
95
|
409 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
410 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
411
|
|
77
|
412 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
413 ABSS_FM<0x20, 20>;
|
|
95
|
414 let AdditionalPredicates = [NotInMicroMips] in{
|
|
|
415 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
416 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
|
|
|
417 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
|
|
|
418 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
|
|
|
419 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
420
|
|
77
|
421 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
|
|
|
422 ABSS_FM<0x20, 17>, FGR_32;
|
|
|
423 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
424 ABSS_FM<0x21, 20>, FGR_32;
|
|
|
425 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
426 ABSS_FM<0x21, 16>, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
427
|
|
121
|
428 let DecoderNamespace = "MipsFP64" in {
|
|
77
|
429 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
|
|
|
430 ABSS_FM<0x20, 17>, FGR_64;
|
|
95
|
431 let AdditionalPredicates = [NotInMicroMips] in{
|
|
|
432 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
|
|
|
433 ABSS_FM<0x20, 21>, FGR_64;
|
|
|
434 }
|
|
77
|
435 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
436 ABSS_FM<0x21, 20>, FGR_64;
|
|
|
437 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
438 ABSS_FM<0x21, 16>, FGR_64;
|
|
|
439 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
|
|
|
440 ABSS_FM<0x21, 21>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
441 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
442
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
443 let isPseudo = 1, isCodeGenOnly = 1 in {
|
|
77
|
444 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
|
|
|
445 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
|
|
|
446 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
|
|
|
447 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
|
|
|
448 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
449 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
450
|
|
121
|
451 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
452 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
|
|
|
453 ABSS_FM<0x5, 16>;
|
|
|
454 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
|
|
|
455 }
|
|
|
456
|
|
77
|
457 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
|
|
|
458 ABSS_FM<0x7, 16>;
|
|
|
459 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
460
|
|
95
|
461 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
|
|
|
462 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
|
|
77
|
463 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
464
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
465 // The odd-numbered registers are only referenced when doing loads,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
466 // stores, and moves between floating-point and integer registers.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
467 // When defining instructions, we reference all 32-bit registers,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
468 // regardless of register aliasing.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
469
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
470 /// Move Control Registers From/To CPU Registers
|
|
120
|
471 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
472 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
|
|
|
473 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
|
|
|
474 }
|
|
77
|
475 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
|
|
|
476 bitconvert>, MFC1_FM<0>;
|
|
121
|
477 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
|
|
|
478 FGR_64 {
|
|
|
479 let DecoderNamespace = "MipsFP64";
|
|
|
480 }
|
|
77
|
481 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
|
|
|
482 bitconvert>, MFC1_FM<4>;
|
|
121
|
483 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
|
|
|
484 FGR_64 {
|
|
|
485 let DecoderNamespace = "MipsFP64";
|
|
|
486 }
|
|
|
487
|
|
120
|
488 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
489 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
|
|
|
490 MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
|
|
|
491 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
|
|
|
492 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
|
|
121
|
493 let DecoderNamespace = "MipsFP64";
|
|
120
|
494 }
|
|
77
|
495 }
|
|
120
|
496 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
497 def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
|
|
|
498 MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
|
|
|
499 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
|
|
|
500 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
|
|
121
|
501 let DecoderNamespace = "MipsFP64";
|
|
120
|
502 }
|
|
77
|
503 }
|
|
120
|
504 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
505 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
|
|
|
506 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
|
|
|
507 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
|
|
|
508 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
|
|
|
509 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
510
|
|
77
|
511 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
512 ABSS_FM<0x6, 16>;
|
|
77
|
513 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
|
|
95
|
514 ABSS_FM<0x6, 17>, FGR_32;
|
|
77
|
515 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
|
|
95
|
516 ABSS_FM<0x6, 17>, FGR_64 {
|
|
121
|
517 let DecoderNamespace = "MipsFP64";
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
518 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
519
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
520 /// Floating Point Memory Instructions
|
|
120
|
521 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
522 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
|
|
|
523 LW_FM<0x31>;
|
|
|
524 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
|
|
|
525 LW_FM<0x39>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
526 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
527
|
|
121
|
528 let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in {
|
|
120
|
529 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
|
|
|
530 LW_FM<0x35>, ISA_MIPS2, FGR_64 {
|
|
|
531 let BaseOpcode = "LDC164";
|
|
|
532 }
|
|
|
533 def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>,
|
|
|
534 LW_FM<0x3d>, ISA_MIPS2, FGR_64;
|
|
|
535 }
|
|
|
536
|
|
|
537 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
538 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,
|
|
|
539 load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 {
|
|
|
540 let BaseOpcode = "LDC132";
|
|
|
541 }
|
|
|
542 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
|
|
|
543 LW_FM<0x3d>, ISA_MIPS2, FGR_32;
|
|
|
544 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
545
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
546 // Indexed loads and stores.
|
|
77
|
547 // Base register + offset register addressing mode (indicated by "x" in the
|
|
|
548 // instruction mnemonic) is disallowed under NaCl.
|
|
|
549 let AdditionalPredicates = [IsNotNaCl] in {
|
|
|
550 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
|
|
|
551 INSN_MIPS4_32R2_NOT_32R6_64R6;
|
|
|
552 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
|
|
|
553 INSN_MIPS4_32R2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
554 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
555
|
|
77
|
556 let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
|
|
|
557 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
|
|
|
558 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
|
|
559 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
|
|
|
560 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
561 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
562
|
|
121
|
563 let DecoderNamespace="MipsFP64" in {
|
|
77
|
564 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
|
|
|
565 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
|
|
566 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
|
|
|
567 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
568 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
569
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
570 // Load/store doubleword indexed unaligned.
|
|
121
|
571 // FIXME: This instruction should not be defined for FGR_32.
|
|
77
|
572 let AdditionalPredicates = [IsNotNaCl] in {
|
|
|
573 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
|
|
|
574 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
|
|
|
575 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
|
|
|
576 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
577 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
578
|
|
121
|
579 let DecoderNamespace="MipsFP64" in {
|
|
77
|
580 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
|
|
|
581 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
|
|
|
582 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
|
|
|
583 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
584 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
585
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
586 /// Floating-point Aritmetic
|
|
77
|
587 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
588 ADDS_FM<0x00, 16>;
|
|
77
|
589 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
|
|
|
590 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
591 ADDS_FM<0x03, 16>;
|
|
77
|
592 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
|
|
|
593 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
594 ADDS_FM<0x02, 16>;
|
|
77
|
595 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
|
|
|
596 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
597 ADDS_FM<0x01, 16>;
|
|
77
|
598 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
599
|
|
77
|
600 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
|
|
121
|
601 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
|
|
77
|
602 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
|
|
121
|
603 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
604
|
|
121
|
605 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
|
|
77
|
606 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
|
|
95
|
607 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
|
77
|
608 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
|
|
95
|
609 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
610 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
611
|
|
77
|
612 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
|
|
121
|
613 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
|
|
77
|
614 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
|
|
121
|
615 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
616
|
|
121
|
617 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
|
|
77
|
618 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
|
|
95
|
619 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
|
77
|
620 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
|
|
95
|
621 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
622 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
623
|
|
121
|
624 let DecoderNamespace = "MipsFP64" in {
|
|
77
|
625 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
|
|
121
|
626 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
|
|
77
|
627 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
|
|
121
|
628 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
629 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
630
|
|
121
|
631 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
|
|
|
632 DecoderNamespace = "MipsFP64" in {
|
|
77
|
633 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
|
|
95
|
634 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
|
77
|
635 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
|
|
95
|
636 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
637 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
638
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
639 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
640 // Floating Point Branch Codes
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
641 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
642 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
643 // They must be kept in synch.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
644 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
645 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
646
|
|
121
|
647 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
648 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
|
|
|
649 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
650 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
|
|
|
651 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
652 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
|
|
|
653 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
654 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
|
|
|
655 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
656
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
657 /// Floating Point Compare
|
|
120
|
658 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
|
|
121
|
659 ISA_MIPS1_NOT_32R6_64R6 {
|
|
|
660
|
|
|
661 // FIXME: This is a required to work around the fact that these instructions
|
|
|
662 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
|
|
|
663 // fcc register set is used directly.
|
|
|
664 bits<3> fcc = 0;
|
|
|
665 }
|
|
120
|
666 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
|
|
121
|
667 ISA_MIPS1_NOT_32R6_64R6, FGR_32 {
|
|
|
668 // FIXME: This is a required to work around the fact that these instructions
|
|
|
669 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
|
|
|
670 // fcc register set is used directly.
|
|
|
671 bits<3> fcc = 0;
|
|
|
672 }
|
|
120
|
673 }
|
|
121
|
674 let DecoderNamespace = "MipsFP64" in
|
|
77
|
675 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
|
|
121
|
676 ISA_MIPS1_NOT_32R6_64R6, FGR_64 {
|
|
|
677 // FIXME: This is a required to work around the fact that thiese instructions
|
|
|
678 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
|
|
|
679 // fcc register set is used directly.
|
|
|
680 bits<3> fcc = 0;
|
|
|
681 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
682
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
683 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
684 // Floating Point Pseudo-Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
685 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
686
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
687 // This pseudo instr gets expanded into 2 mtc1 instrs after register
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
688 // allocation.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
689 class BuildPairF64Base<RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
690 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
|
|
120
|
691 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))],
|
|
|
692 II_MTC1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
693
|
|
95
|
694 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
|
|
|
695 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
696
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
697 // This pseudo instr gets expanded into 2 mfc1 instrs after register
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
698 // allocation.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
699 // if n is 0, lower part of src is extracted.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
700 // if n is 1, higher part of src is extracted.
|
|
120
|
701 // This node has associated scheduling information as the pre RA scheduler
|
|
|
702 // asserts otherwise.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
703 class ExtractElementF64Base<RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
704 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
|
|
120
|
705 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))],
|
|
|
706 II_MFC1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
707
|
|
95
|
708 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
|
|
|
709 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
710
|
|
120
|
711 def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
|
|
|
712 (ins FGR32Opnd:$fs, GPR32Opnd:$rs),
|
|
|
713 "trunc.w.s\t$fd, $fs, $rs">;
|
|
|
714
|
|
|
715 def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
|
|
|
716 (ins AFGR64Opnd:$fs, GPR32Opnd:$rs),
|
|
|
717 "trunc.w.d\t$fd, $fs, $rs">,
|
|
|
718 FGR_32, HARDFLOAT;
|
|
|
719
|
|
|
720 def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
|
|
|
721 (ins FGR64Opnd:$fs, GPR32Opnd:$rs),
|
|
|
722 "trunc.w.d\t$fd, $fs, $rs">,
|
|
|
723 FGR_64, HARDFLOAT;
|
|
|
724
|
|
121
|
725 def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
|
|
|
726 (ins imm64:$fpimm),
|
|
|
727 "li.s\t$rd, $fpimm">;
|
|
|
728
|
|
|
729 def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd),
|
|
|
730 (ins imm64:$fpimm),
|
|
|
731 "li.s\t$rd, $fpimm">,
|
|
|
732 HARDFLOAT;
|
|
|
733
|
|
|
734 def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
|
|
|
735 (ins imm64:$fpimm),
|
|
|
736 "li.d\t$rd, $fpimm">;
|
|
|
737
|
|
|
738 def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd),
|
|
|
739 (ins imm64:$fpimm),
|
|
|
740 "li.d\t$rd, $fpimm">,
|
|
|
741 FGR_32, HARDFLOAT;
|
|
|
742
|
|
|
743 def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd),
|
|
|
744 (ins imm64:$fpimm),
|
|
|
745 "li.d\t$rd, $fpimm">,
|
|
|
746 FGR_64, HARDFLOAT;
|
|
|
747
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
748 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
749 // InstAliases.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
750 //===----------------------------------------------------------------------===//
|
|
120
|
751 def : MipsInstAlias
|
|
|
752 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
|
|
|
753 ISA_MIPS2, HARDFLOAT;
|
|
|
754 def : MipsInstAlias
|
|
|
755 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
|
|
|
756 FGR_32, ISA_MIPS2, HARDFLOAT;
|
|
|
757 def : MipsInstAlias
|
|
|
758 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>,
|
|
|
759 FGR_64, ISA_MIPS2, HARDFLOAT;
|
|
|
760
|
|
|
761 def : MipsInstAlias
|
|
|
762 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
|
|
|
763 ISA_MIPS2, HARDFLOAT;
|
|
|
764 def : MipsInstAlias
|
|
|
765 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
|
|
|
766 FGR_32, ISA_MIPS2, HARDFLOAT;
|
|
|
767 def : MipsInstAlias
|
|
|
768 <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>,
|
|
|
769 FGR_64, ISA_MIPS2, HARDFLOAT;
|
|
121
|
770
|
|
|
771 multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> {
|
|
|
772 def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"),
|
|
|
773 (!cast<Instruction>("C_F_"#NAME) FCC0,
|
|
|
774 RC:$fs, RC:$ft), 1>;
|
|
|
775 def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"),
|
|
|
776 (!cast<Instruction>("C_UN_"#NAME) FCC0,
|
|
|
777 RC:$fs, RC:$ft), 1>;
|
|
|
778 def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"),
|
|
|
779 (!cast<Instruction>("C_EQ_"#NAME) FCC0,
|
|
|
780 RC:$fs, RC:$ft), 1>;
|
|
|
781 def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"),
|
|
|
782 (!cast<Instruction>("C_UEQ_"#NAME) FCC0,
|
|
|
783 RC:$fs, RC:$ft), 1>;
|
|
|
784 def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"),
|
|
|
785 (!cast<Instruction>("C_OLT_"#NAME) FCC0,
|
|
|
786 RC:$fs, RC:$ft), 1>;
|
|
|
787 def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"),
|
|
|
788 (!cast<Instruction>("C_ULT_"#NAME) FCC0,
|
|
|
789 RC:$fs, RC:$ft), 1>;
|
|
|
790 def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"),
|
|
|
791 (!cast<Instruction>("C_OLE_"#NAME) FCC0,
|
|
|
792 RC:$fs, RC:$ft), 1>;
|
|
|
793 def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"),
|
|
|
794 (!cast<Instruction>("C_ULE_"#NAME) FCC0,
|
|
|
795 RC:$fs, RC:$ft), 1>;
|
|
|
796 def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"),
|
|
|
797 (!cast<Instruction>("C_SF_"#NAME) FCC0,
|
|
|
798 RC:$fs, RC:$ft), 1>;
|
|
|
799 def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"),
|
|
|
800 (!cast<Instruction>("C_NGLE_"#NAME) FCC0,
|
|
|
801 RC:$fs, RC:$ft), 1>;
|
|
|
802 def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"),
|
|
|
803 (!cast<Instruction>("C_SEQ_"#NAME) FCC0,
|
|
|
804 RC:$fs, RC:$ft), 1>;
|
|
|
805 def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"),
|
|
|
806 (!cast<Instruction>("C_NGL_"#NAME) FCC0,
|
|
|
807 RC:$fs, RC:$ft), 1>;
|
|
|
808 def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"),
|
|
|
809 (!cast<Instruction>("C_LT_"#NAME) FCC0,
|
|
|
810 RC:$fs, RC:$ft), 1>;
|
|
|
811 def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"),
|
|
|
812 (!cast<Instruction>("C_NGE_"#NAME) FCC0,
|
|
|
813 RC:$fs, RC:$ft), 1>;
|
|
|
814 def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"),
|
|
|
815 (!cast<Instruction>("C_LE_"#NAME) FCC0,
|
|
|
816 RC:$fs, RC:$ft), 1>;
|
|
|
817 def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"),
|
|
|
818 (!cast<Instruction>("C_NGT_"#NAME) FCC0,
|
|
|
819 RC:$fs, RC:$ft), 1>;
|
|
|
820 }
|
|
|
821
|
|
|
822 multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString,
|
|
|
823 Instruction BCFalse, string BCFalseString> {
|
|
|
824 def : MipsInstAlias<!strconcat(BCTrueString, " $offset"),
|
|
|
825 (BCTrue FCC0, brtarget:$offset), 1>;
|
|
|
826
|
|
|
827 def : MipsInstAlias<!strconcat(BCFalseString, " $offset"),
|
|
|
828 (BCFalse FCC0, brtarget:$offset), 1>;
|
|
|
829 }
|
|
|
830
|
|
|
831 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
832 defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT,
|
|
|
833 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
834 defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT,
|
|
|
835 ISA_MIPS1_NOT_32R6_64R6, FGR_32;
|
|
|
836 defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,
|
|
|
837 ISA_MIPS1_NOT_32R6_64R6, FGR_64;
|
|
|
838
|
|
|
839 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6,
|
|
|
840 HARDFLOAT;
|
|
|
841 defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6,
|
|
|
842 HARDFLOAT;
|
|
|
843 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
844 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
845 // Floating Point Patterns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
846 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
847 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
848 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
849
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
850 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
851 (PseudoCVT_S_W GPR32Opnd:$src)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
852 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
853 (TRUNC_W_S FGR32Opnd:$src)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
854
|
|
121
|
855 def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src),
|
|
|
856 (MTC1_D64 GPR32Opnd:$src)>, FGR_64;
|
|
|
857
|
|
77
|
858 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
|
|
859 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
|
|
|
860 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
|
|
|
861 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
|
|
120
|
862 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),
|
|
77
|
863 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
|
|
120
|
864 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
|
|
77
|
865 (CVT_D32_S FGR32Opnd:$src)>, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
866
|
|
77
|
867 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
|
|
|
868 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
869
|
|
77
|
870 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
|
|
871 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
|
|
|
872 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
|
|
|
873 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
|
|
|
874 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
|
|
|
875 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
876
|
|
77
|
877 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
|
|
878 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
|
|
|
879 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
|
|
880 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
|
|
|
881 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
|
|
882 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
883
|
|
120
|
884 def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
|
|
77
|
885 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
|
|
120
|
886 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
|
|
77
|
887 (CVT_D64_S FGR32Opnd:$src)>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
888
|
|
121
|
889 // To generate NMADD and NMSUB instructions when fneg node is present
|
|
|
890 multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> {
|
|
|
891 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)),
|
|
|
892 (Nmadd RC:$fr, RC:$fs, RC:$ft)>;
|
|
|
893 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)),
|
|
|
894 (Nmsub RC:$fr, RC:$fs, RC:$ft)>;
|
|
|
895 }
|
|
|
896
|
|
|
897 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
|
|
|
898 defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
|
|
899 defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>, FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
|
|
900 defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>, FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
|
|
901 }
|
|
|
902
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
903 // Patterns for loads/stores with a reg+imm operand.
|
|
120
|
904 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
905 let AddedComplexity = 40 in {
|
|
|
906 def : LoadRegImmPat<LWC1, f32, load>;
|
|
|
907 def : StoreRegImmPat<SWC1, f32>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
908
|
|
120
|
909 def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
|
|
|
910 def : StoreRegImmPat<SDC164, f64>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
911
|
|
120
|
912 def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
|
|
|
913 def : StoreRegImmPat<SDC1, f64>, FGR_32;
|
|
|
914 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
915 }
|
