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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
2 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
3 // The LLVM Compiler Infrastructure
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
4 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
5 // This file is distributed under the University of Illinois Open Source
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
6 // License. See LICENSE.TXT for details.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
7 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
8 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
9 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
10 // This file describes the Mips FPU instruction set.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
11 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
12 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
13
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
14 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
15 // Floating Point Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
16 // ------------------------
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
17 // * 64bit fp:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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18 // - 32 64-bit registers (default mode)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
19 // - 16 even 32-bit registers (32-bit compatible mode) for
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
20 // single and double access.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
21 // * 32bit fp:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
22 // - 16 even 32-bit registers - single and double (aliased)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
23 // - 32 32-bit registers (within single-only mode)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
24 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
25
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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26 // Floating Point Compare and Branch
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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28 SDTCisVT<1, i32>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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29 SDTCisVT<2, OtherVT>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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30 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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31 SDTCisVT<2, i32>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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32 def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
33 SDTCisSameAs<1, 3>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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34 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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35 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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36 SDTCisVT<1, i32>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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37 SDTCisSameAs<1, 2>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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38 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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39 SDTCisVT<1, f64>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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40 SDTCisVT<2, i32>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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41
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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42 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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43 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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44 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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45 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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46 [SDNPHasChain, SDNPOptInGlue]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
47 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
|
48 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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49 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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50 SDT_MipsExtractElementF64>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
51
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
52 // Operand for printing out a condition code.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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53 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
|
54 def condcode : Operand<i32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
55
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
56 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
57 // Feature predicates.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
58 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
59
|
|
77
|
60 def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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61 AssemblerPredicate<"FeatureFP64Bit">;
|
|
77
|
62 def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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63 AssemblerPredicate<"!FeatureFP64Bit">;
|
|
77
|
64 def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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65 AssemblerPredicate<"FeatureSingleFloat">;
|
|
77
|
66 def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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67 AssemblerPredicate<"!FeatureSingleFloat">;
|
|
95
|
68 def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">,
|
|
|
69 AssemblerPredicate<"!FeatureSoftFloat">;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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70
|
|
77
|
71 //===----------------------------------------------------------------------===//
|
|
|
72 // Mips FGR size adjectives.
|
|
|
73 // They are mutually exclusive.
|
|
|
74 //===----------------------------------------------------------------------===//
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|
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75
|
|
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76 class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
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|
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77 class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
|
|
95
|
78 class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; }
|
|
77
|
79
|
|
|
80 //===----------------------------------------------------------------------===//
|
|
|
81
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
82 // FP immediate patterns.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
83 def fpimm0 : PatLeaf<(fpimm), [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
84 return N->isExactlyValue(+0.0);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
85 }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
86
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
87 def fpimm0neg : PatLeaf<(fpimm), [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
88 return N->isExactlyValue(-0.0);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
89 }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
90
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
91 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
92 // Instruction Class Templates
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
93 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
94 // A set of multiclasses is used to address the register usage.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
95 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
96 // S32 - single precision in 16 32bit even fp registers
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
97 // single precision in 32 32bit fp registers in SingleOnly mode
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
98 // S64 - single precision in 32 64bit fp registers (In64BitMode)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
99 // D32 - double precision in 16 32bit even fp registers
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
100 // D64 - double precision in 32 64bit fp registers (In64BitMode)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
101 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
102 // Only S32 and D32 are supported right now.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
103 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
104 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
105 SDPatternOperator OpNode= null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
106 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
107 !strconcat(opstr, "\t$fd, $fs, $ft"),
|
|
95
|
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
|
|
|
109 HARDFLOAT {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
110 let isCommutable = IsComm;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
111 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
112
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
113 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
114 SDPatternOperator OpNode = null_frag> {
|
|
95
|
115 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
|
|
|
116 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
117 string DecoderNamespace = "Mips64";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
118 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
119 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
120
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
|
|
77
|
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
|
|
95
|
125 HARDFLOAT,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
126 NeverHasSideEffects;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
127
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
128 multiclass ABSS_M<string opstr, InstrItinClass Itin,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
129 SDPatternOperator OpNode= null_frag> {
|
|
77
|
130 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
|
|
95
|
131 FGR_32;
|
|
|
132 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
133 string DecoderNamespace = "Mips64";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
134 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
135 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
136
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
137 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
|
|
95
|
138 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
|
|
100
|
139 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
140 let DecoderNamespace = "Mips64";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
141 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
142 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
143
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
144 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
145 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
|
|
95
|
147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
148
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
149 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
150 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
|
|
95
|
152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
|
|
77
|
153
|
|
|
154 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
|
|
155 InstrItinClass Itin> :
|
|
|
156 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
|
|
95
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157 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT {
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77
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158 // $fs_in is part of a white lie to work around a widespread bug in the FPU
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|
|
159 // implementation. See expandBuildPairF64 for details.
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160 let Constraints = "$fs = $fs_in";
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161 }
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162
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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163 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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164 SDPatternOperator OpNode= null_frag> :
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165 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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95
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166 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
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167 HARDFLOAT {
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168 let DecoderMethod = "DecodeFMem";
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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169 let mayLoad = 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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170 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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171
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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172 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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173 SDPatternOperator OpNode= null_frag> :
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174 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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95
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175 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
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176 let DecoderMethod = "DecodeFMem";
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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177 let mayStore = 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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178 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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179
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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180 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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181 SDPatternOperator OpNode = null_frag> :
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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182 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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183 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
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77
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184 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
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95
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185 FrmFR, opstr>, HARDFLOAT;
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186
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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187 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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188 SDPatternOperator OpNode = null_frag> :
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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189 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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190 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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191 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
|
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95
|
192 Itin, FrmFR, opstr>, HARDFLOAT;
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parents:
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193
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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194 class LWXC1_FT<string opstr, RegisterOperand DRC,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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195 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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196 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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197 !strconcat(opstr, "\t$fd, ${index}(${base})"),
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77
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198 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
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95
|
199 FrmFI, opstr>, HARDFLOAT {
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200 let AddedComplexity = 20;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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201 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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202
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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203 class SWXC1_FT<string opstr, RegisterOperand DRC,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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204 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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205 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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206 !strconcat(opstr, "\t$fs, ${index}(${base})"),
|
|
77
|
207 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
|
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95
|
208 FrmFI, opstr>, HARDFLOAT {
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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209 let AddedComplexity = 20;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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210 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
211
|
|
77
|
212 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
|
|
83
|
213 SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
|
|
77
|
214 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
215 !strconcat(opstr, "\t$fcc, $offset"),
|
|
77
|
216 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
|
|
95
|
217 FrmFI, opstr>, HARDFLOAT {
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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218 let isBranch = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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219 let isTerminator = 1;
|
|
83
|
220 let hasDelaySlot = DelaySlot;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
221 let Defs = [AT];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
222 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
223
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
224 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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225 SDPatternOperator OpNode = null_frag> :
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
226 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
227 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
|
|
77
|
228 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
|
|
95
|
229 !strconcat("c.$cond.", typestr)>, HARDFLOAT {
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
230 let Defs = [FCC0];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
231 let isCodeGenOnly = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
232 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
233
|
|
77
|
234 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
|
|
|
235 InstrItinClass itin> :
|
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parents:
diff
changeset
|
236 InstSE<(outs), (ins RC:$fs, RC:$ft),
|
|
77
|
237 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin,
|
|
95
|
238 FrmFR>, HARDFLOAT;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
239
|
|
77
|
240 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
|
|
|
241 InstrItinClass itin> {
|
|
|
242 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>;
|
|
|
243 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>;
|
|
|
244 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>;
|
|
|
245 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>;
|
|
|
246 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>;
|
|
|
247 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>;
|
|
|
248 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>;
|
|
|
249 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>;
|
|
|
250 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>;
|
|
|
251 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>;
|
|
|
252 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>;
|
|
|
253 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>;
|
|
|
254 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>;
|
|
|
255 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>;
|
|
|
256 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>;
|
|
|
257 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
258 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
259
|
|
77
|
260 defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
261 defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
|
|
95
|
262 FGR_32;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
263 let DecoderNamespace = "Mips64" in
|
|
77
|
264 defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
|
|
95
|
265 FGR_64;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
266
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
267 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
268 // Floating Point Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
269 //===----------------------------------------------------------------------===//
|
|
100
|
270 def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
|
|
77
|
271 ABSS_FM<0xc, 16>, ISA_MIPS2;
|
|
100
|
272 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
|
|
95
|
273 def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
|
|
77
|
274 ABSS_FM<0xd, 16>, ISA_MIPS2;
|
|
95
|
275 def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
|
|
77
|
276 ABSS_FM<0xe, 16>, ISA_MIPS2;
|
|
95
|
277 def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
|
|
77
|
278 ABSS_FM<0xf, 16>, ISA_MIPS2;
|
|
|
279 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
280 ABSS_FM<0x24, 16>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
281
|
|
77
|
282 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
|
|
|
283 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
|
|
|
284 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
|
|
|
285 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
286
|
|
77
|
287 let DecoderNamespace = "Mips64" in {
|
|
100
|
288 let AdditionalPredicates = [NotInMicroMips] in {
|
|
77
|
289 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
|
|
|
290 ABSS_FM<0x8, 16>, FGR_64;
|
|
|
291 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
|
|
|
292 ABSS_FM<0x8, 17>, FGR_64;
|
|
|
293 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
|
|
|
294 ABSS_FM<0x9, 16>, FGR_64;
|
|
|
295 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
|
|
|
296 ABSS_FM<0x9, 17>, FGR_64;
|
|
|
297 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
|
|
|
298 ABSS_FM<0xa, 16>, FGR_64;
|
|
|
299 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
|
|
|
300 ABSS_FM<0xa, 17>, FGR_64;
|
|
|
301 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
|
|
|
302 ABSS_FM<0xb, 16>, FGR_64;
|
|
|
303 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
|
|
|
304 ABSS_FM<0xb, 17>, FGR_64;
|
|
95
|
305 }
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
306 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
307
|
|
77
|
308 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
309 ABSS_FM<0x20, 20>;
|
|
95
|
310 let AdditionalPredicates = [NotInMicroMips] in{
|
|
|
311 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
312 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
|
|
|
313 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
|
|
|
314 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
|
|
|
315 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
316
|
|
77
|
317 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
|
|
|
318 ABSS_FM<0x20, 17>, FGR_32;
|
|
|
319 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
320 ABSS_FM<0x21, 20>, FGR_32;
|
|
|
321 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
322 ABSS_FM<0x21, 16>, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
323
|
|
77
|
324 let DecoderNamespace = "Mips64" in {
|
|
|
325 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
|
|
|
326 ABSS_FM<0x20, 17>, FGR_64;
|
|
95
|
327 let AdditionalPredicates = [NotInMicroMips] in{
|
|
|
328 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
|
|
|
329 ABSS_FM<0x20, 21>, FGR_64;
|
|
|
330 }
|
|
77
|
331 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
332 ABSS_FM<0x21, 20>, FGR_64;
|
|
|
333 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
|
|
|
334 ABSS_FM<0x21, 16>, FGR_64;
|
|
|
335 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
|
|
|
336 ABSS_FM<0x21, 21>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
337 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
338
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
339 let isPseudo = 1, isCodeGenOnly = 1 in {
|
|
77
|
340 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
|
|
|
341 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
|
|
|
342 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
|
|
|
343 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
|
|
|
344 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
345 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
346
|
|
77
|
347 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
|
|
|
348 ABSS_FM<0x5, 16>;
|
|
|
349 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
|
|
|
350 ABSS_FM<0x7, 16>;
|
|
|
351 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
|
|
|
352 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
353
|
|
95
|
354 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
|
|
|
355 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
|
|
77
|
356 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
357
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
358 // The odd-numbered registers are only referenced when doing loads,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
359 // stores, and moves between floating-point and integer registers.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
360 // When defining instructions, we reference all 32-bit registers,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
361 // regardless of register aliasing.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
362
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
363 /// Move Control Registers From/To CPU Registers
|
|
77
|
364 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
|
|
|
365 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
|
|
|
366 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
|
|
|
367 bitconvert>, MFC1_FM<0>;
|
|
|
368 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
|
|
|
369 bitconvert>, MFC1_FM<4>;
|
|
|
370 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
|
|
95
|
371 MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
|
|
77
|
372 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
|
|
95
|
373 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
|
|
77
|
374 let DecoderNamespace = "Mips64";
|
|
|
375 }
|
|
|
376 def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
|
|
95
|
377 MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
|
|
77
|
378 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
|
|
95
|
379 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
|
|
77
|
380 let DecoderNamespace = "Mips64";
|
|
|
381 }
|
|
|
382 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
|
|
|
383 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
|
|
|
384 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
|
|
|
385 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
386
|
|
77
|
387 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
388 ABSS_FM<0x6, 16>;
|
|
77
|
389 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
|
|
95
|
390 ABSS_FM<0x6, 17>, FGR_32;
|
|
77
|
391 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
|
|
95
|
392 ABSS_FM<0x6, 17>, FGR_64 {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
393 let DecoderNamespace = "Mips64";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
394 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
395
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
396 /// Floating Point Memory Instructions
|
|
77
|
397 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
|
|
|
398 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
399
|
|
77
|
400 let DecoderNamespace = "Mips64" in {
|
|
|
401 def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2,
|
|
|
402 FGR_64;
|
|
|
403 def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2,
|
|
|
404 FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
405 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
406
|
|
77
|
407 def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
|
|
|
408 ISA_MIPS2, FGR_32;
|
|
|
409 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
|
|
|
410 ISA_MIPS2, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
411
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
412 // Indexed loads and stores.
|
|
77
|
413 // Base register + offset register addressing mode (indicated by "x" in the
|
|
|
414 // instruction mnemonic) is disallowed under NaCl.
|
|
|
415 let AdditionalPredicates = [IsNotNaCl] in {
|
|
|
416 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
|
|
|
417 INSN_MIPS4_32R2_NOT_32R6_64R6;
|
|
|
418 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
|
|
|
419 INSN_MIPS4_32R2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
420 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
421
|
|
77
|
422 let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
|
|
|
423 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
|
|
|
424 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
|
|
425 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
|
|
|
426 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
427 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
428
|
|
77
|
429 let DecoderNamespace="Mips64" in {
|
|
|
430 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
|
|
|
431 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
|
|
432 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
|
|
|
433 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
434 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
435
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
436 // Load/store doubleword indexed unaligned.
|
|
77
|
437 let AdditionalPredicates = [IsNotNaCl] in {
|
|
|
438 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
|
|
|
439 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
|
|
|
440 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
|
|
|
441 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
442 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
443
|
|
77
|
444 let DecoderNamespace="Mips64" in {
|
|
|
445 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
|
|
|
446 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
|
|
|
447 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
|
|
|
448 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
449 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
450
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
451 /// Floating-point Aritmetic
|
|
77
|
452 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
453 ADDS_FM<0x00, 16>;
|
|
77
|
454 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
|
|
|
455 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
456 ADDS_FM<0x03, 16>;
|
|
77
|
457 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
|
|
|
458 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
459 ADDS_FM<0x02, 16>;
|
|
77
|
460 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
|
|
|
461 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
462 ADDS_FM<0x01, 16>;
|
|
77
|
463 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
464
|
|
77
|
465 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
|
|
95
|
466 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
|
77
|
467 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
|
|
95
|
468 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
469
|
|
77
|
470 let AdditionalPredicates = [NoNaNsFPMath] in {
|
|
|
471 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
|
|
95
|
472 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
|
77
|
473 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
|
|
95
|
474 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
475 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
476
|
|
77
|
477 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
|
|
95
|
478 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
|
77
|
479 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
|
|
95
|
480 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
481
|
|
77
|
482 let AdditionalPredicates = [NoNaNsFPMath] in {
|
|
|
483 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
|
|
95
|
484 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
|
77
|
485 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
|
|
95
|
486 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
487 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
488
|
|
95
|
489 let DecoderNamespace = "Mips64" in {
|
|
77
|
490 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
|
|
95
|
491 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
|
77
|
492 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
|
|
95
|
493 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
494 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
495
|
|
77
|
496 let AdditionalPredicates = [NoNaNsFPMath],
|
|
95
|
497 DecoderNamespace = "Mips64" in {
|
|
77
|
498 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
|
|
95
|
499 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
|
77
|
500 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
|
|
95
|
501 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
502 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
503
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
504 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
505 // Floating Point Branch Codes
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
506 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
507 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
508 // They must be kept in synch.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
509 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
510 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
511
|
|
95
|
512 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
|
|
77
|
513 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
|
|
95
|
514 def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
|
|
83
|
515 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
|
|
95
|
516 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
|
|
77
|
517 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
|
95
|
518 def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
|
|
83
|
519 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
520
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
521 /// Floating Point Compare
|
|
77
|
522 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
|
|
|
523 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
524 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
|
|
95
|
525 ISA_MIPS1_NOT_32R6_64R6, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
526 let DecoderNamespace = "Mips64" in
|
|
77
|
527 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
|
|
95
|
528 ISA_MIPS1_NOT_32R6_64R6, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
529
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
530 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
531 // Floating Point Pseudo-Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
532 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
533
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
534 // This pseudo instr gets expanded into 2 mtc1 instrs after register
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
535 // allocation.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
536 class BuildPairF64Base<RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
537 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
538 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
539
|
|
95
|
540 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
|
|
|
541 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
542
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
543 // This pseudo instr gets expanded into 2 mfc1 instrs after register
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
544 // allocation.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
545 // if n is 0, lower part of src is extracted.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
546 // if n is 1, higher part of src is extracted.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
547 class ExtractElementF64Base<RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
548 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
549 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
550
|
|
95
|
551 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
|
|
|
552 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
553
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
554 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
555 // InstAliases.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
556 //===----------------------------------------------------------------------===//
|
|
77
|
557 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
|
|
95
|
558 ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
|
|
83
|
559 def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
|
|
95
|
560 ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT;
|
|
77
|
561 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
|
|
95
|
562 ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
|
|
83
|
563 def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
|
|
95
|
564 ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
565
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
566 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
567 // Floating Point Patterns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
568 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
569 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
570 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
571
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
572 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
573 (PseudoCVT_S_W GPR32Opnd:$src)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
574 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
575 (TRUNC_W_S FGR32Opnd:$src)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
576
|
|
77
|
577 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
|
|
578 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
|
|
|
579 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
|
|
|
580 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
|
|
|
581 def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
|
|
|
582 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
|
|
|
583 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
|
|
|
584 (CVT_D32_S FGR32Opnd:$src)>, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
585
|
|
77
|
586 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
|
|
|
587 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
588
|
|
77
|
589 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
|
|
590 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
|
|
|
591 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
|
|
|
592 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
|
|
|
593 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
|
|
|
594 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
595
|
|
77
|
596 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
|
|
597 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
|
|
|
598 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
|
|
599 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
|
|
|
600 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
|
|
601 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
602
|
|
77
|
603 def : MipsPat<(f32 (fround FGR64Opnd:$src)),
|
|
|
604 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
|
|
|
605 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
|
|
|
606 (CVT_D64_S FGR32Opnd:$src)>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
607
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
608 // Patterns for loads/stores with a reg+imm operand.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
609 let AddedComplexity = 40 in {
|
|
77
|
610 def : LoadRegImmPat<LWC1, f32, load>;
|
|
|
611 def : StoreRegImmPat<SWC1, f32>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
612
|
|
77
|
613 def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
|
|
|
614 def : StoreRegImmPat<SDC164, f64>, FGR_64;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
615
|
|
77
|
616 def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
|
|
|
617 def : StoreRegImmPat<SDC1, f64>, FGR_32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
618 }
|
