annotate lib/Target/Mips/MipsMTInstrFormats.td @ 131:f476a9ba4795

http://llvm.org/svn/llvm-project/compiler-rt/trunk compiler-rt
author mir3636
date Fri, 16 Feb 2018 21:02:11 +0900
parents 803732b1fca8
children 3a76565eade5
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1 //===-- MipsMTInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 //===----------------------------------------------------------------------===//
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11 // Describe the MIPS MT instructions format
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12 //
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13 // opcode - operation code.
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14 // rt - destination register
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15 //
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16 //===----------------------------------------------------------------------===//
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17
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18 class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
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19 PredicateControl {
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20 let DecoderNamespace = "Mips";
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21 let EncodingPredicates = [HasStdEnc];
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22 }
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23
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24 class OPCODE1<bits<1> Val> {
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25 bits<1> Value = Val;
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26 }
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27
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28 def OPCODE_SC_D : OPCODE1<0b0>;
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29 def OPCODE_SC_E : OPCODE1<0b1>;
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30
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31 class FIELD5<bits<5> Val> {
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32 bits<5> Value = Val;
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33 }
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34
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35 def FIELD5_1_DMT_EMT : FIELD5<0b00001>;
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36 def FIELD5_2_DMT_EMT : FIELD5<0b01111>;
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37 def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
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38
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39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
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40 bits<32> Inst;
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41
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42 bits<5> rt;
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43 let Inst{31-26} = 0b010000; // COP0
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44 let Inst{25-21} = 0b01011; // MFMC0
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45 let Inst{20-16} = rt;
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46 let Inst{15-11} = Op1.Value;
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47 let Inst{10-6} = Op2.Value;
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48 let Inst{5} = sc.Value;
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49 let Inst{4-3} = 0b00;
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50 let Inst{2-0} = 0b001;
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51 }
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52
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53 class SPECIAL3_MT_FORK : MipsMTInst {
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54 bits<32> Inst;
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55
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56 bits<5> rs;
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57 bits<5> rt;
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58 bits<5> rd;
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59 let Inst{31-26} = 0b011111; // SPECIAL3
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60 let Inst{25-21} = rs;
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61 let Inst{20-16} = rt;
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62 let Inst{15-11} = rd;
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63 let Inst{10-6} = 0b00000;
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64 let Inst{5-0} = 0b001000; // FORK
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65 }
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66
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67 class SPECIAL3_MT_YIELD : MipsMTInst {
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68 bits<32> Inst;
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69
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70 bits<5> rs;
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71 bits<5> rd;
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72 let Inst{31-26} = 0b011111; // SPECIAL3
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73 let Inst{25-21} = rs;
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74 let Inst{20-16} = 0b00000;
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75 let Inst{15-11} = rd;
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76 let Inst{10-6} = 0b00000;
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77 let Inst{5-0} = 0b001001; // FORK
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78 }