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150
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1 // RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s -o %t
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2 // RUN: FileCheck --check-prefix=ADD %s < %t
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3 // RUN: FileCheck --check-prefix=ADDINT %s < %t
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4 // RUN: FileCheck --check-prefix=SUB %s < %t
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5 // RUN: FileCheck --check-prefix=MULINT %s < %t
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6
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7 include "llvm/Target/Target.td"
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8
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9 def TestInstrInfo : InstrInfo;
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10 def TestTarget : Target {
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11 let InstructionSet = TestInstrInfo;
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12 }
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13
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14 class TestEncoding : Instruction {
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15 field bits<32> Inst;
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16 }
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17
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18 class TestReg<int index> : Register<"R"#index, []> {
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207
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19 let HWEncoding{15...4} = 0;
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20 let HWEncoding{3...0} = !cast<bits<4>>(index);
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150
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21 }
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207
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22 foreach i = 0...15 in
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150
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23 def "R"#i : TestReg<i>;
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24
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25 def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 15)>;
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26
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27 def IntOperand: Operand<i32>;
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28 def OptionalIntOperand: OperandWithDefaultOps<i32, (ops (i32 0))>;
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29
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30 class RRI<string Mnemonic, bits<4> Opcode> : TestEncoding {
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31 dag OutOperandList = (outs Reg:$dest);
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32 dag InOperandList = (ins Reg:$src1, Reg:$src2, OptionalIntOperand:$imm);
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33 string AsmString = Mnemonic # " $dest1, $src1, $src2, #$imm";
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34 string AsmVariantName = "";
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35 field bits<4> dest;
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36 field bits<4> src1;
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37 field bits<4> src2;
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38 field bits<16> imm;
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207
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39 let Inst{31...28} = Opcode;
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40 let Inst{27...24} = dest;
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41 let Inst{23...20} = src1;
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42 let Inst{19...16} = src2;
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43 let Inst{15...0} = imm;
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150
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44 }
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45
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46 def AddRRI : RRI<"add", 0b0001>;
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47
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48 // I define one of these intrinsics with IntrNoMem and the other
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49 // without it, so that they'll match different top-level DAG opcodes
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50 // (INTRINSIC_WO_CHAIN and INTRINSIC_W_CHAIN), which makes the
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51 // FileCheck-herding easier, because every case I want to detect
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52 // should show up as a separate top-level switch element.
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53 def int_addplus1 : Intrinsic<
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54 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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55 def int_mul3 : Intrinsic<
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56 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty]>;
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57
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58 def AddPat : Pat<(add i32:$x, i32:$y),
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59 (AddRRI Reg:$x, Reg:$y)>;
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60 def Add1Pat : Pat<(int_addplus1 i32:$x, i32:$y),
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61 (AddRRI Reg:$x, Reg:$y, (i32 1))>;
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62
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63 def SubRRI : RRI<"sub", 0b0010> {
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64 let Pattern = [(set Reg:$dest, (sub Reg:$src1, Reg:$src2))];
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65 }
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66
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67 def MulRRI : RRI<"mul", 0b0011> {
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68 let Pattern = [(set Reg:$dest, (int_mul3 Reg:$src1, Reg:$src2, i32:$imm))];
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69 }
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70
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71 def MulIRR : RRI<"mul2", 0b0100> {
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72 let InOperandList = (ins OptionalIntOperand:$imm, Reg:$src1, Reg:$src2);
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73 }
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74 def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>;
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75
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76 // ADD: SwitchOpcode{{.*}}TARGET_VAL(ISD::ADD)
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77 // ADD-NEXT: OPC_RecordChild0
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78 // ADD-NEXT: OPC_RecordChild1
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79 // ADD-NEXT: OPC_EmitInteger, MVT::i32, 0
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80 // ADD-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI)
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81
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82 // ADDINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_WO_CHAIN)
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83 // ADDINT-NEXT: OPC_CheckChild0Integer
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84 // ADDINT-NEXT: OPC_RecordChild1
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85 // ADDINT-NEXT: OPC_RecordChild2
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207
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86 // ADDINT-NEXT: OPC_EmitInteger, MVT::i32, 2
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150
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87 // ADDINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI)
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88
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89 // SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB)
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90 // SUB-NEXT: OPC_RecordChild0
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91 // SUB-NEXT: OPC_RecordChild1
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92 // SUB-NEXT: OPC_EmitInteger, MVT::i32, 0
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93 // SUB-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::SubRRI)
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94
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95 // MULINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_W_CHAIN)
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96 // MULINT-NEXT: OPC_RecordNode
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97 // MULINT-NEXT: OPC_CheckChild1Integer
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98 // MULINT-NEXT: OPC_RecordChild2
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99 // MULINT-NEXT: OPC_RecordChild3
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100 // MULINT-NEXT: OPC_RecordChild4
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101 // MULINT-NEXT: OPC_EmitMergeInputChains
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102 // MULINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::MulRRI)
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103
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104 // MUL: SwitchOpcode{{.*}}TARGET_VAL(ISD::MUL)
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105 // MUL-NEXT: OPC_EmitInteger, MVT::i32, 0
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106 // MUL-NEXT: OPC_RecordChild0
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107 // MUL-NEXT: OPC_RecordChild1
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108 // MUL-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::MulRRI)
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