Mercurial > hg > CbC > CbC_llvm
diff llvm/test/TableGen/DAGDefaultOps.td @ 207:2e18cbf3894f
LLVM12
| author | Shinji KONO <kono@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 08 Jun 2021 06:07:14 +0900 |
| parents | 1d019706d866 |
| children |
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--- a/llvm/test/TableGen/DAGDefaultOps.td Mon May 25 11:55:54 2020 +0900 +++ b/llvm/test/TableGen/DAGDefaultOps.td Tue Jun 08 06:07:14 2021 +0900 @@ -16,10 +16,10 @@ } class TestReg<int index> : Register<"R"#index, []> { - let HWEncoding{15-4} = 0; - let HWEncoding{3-0} = !cast<bits<4>>(index); + let HWEncoding{15...4} = 0; + let HWEncoding{3...0} = !cast<bits<4>>(index); } -foreach i = 0-15 in +foreach i = 0...15 in def "R"#i : TestReg<i>; def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 15)>; @@ -36,11 +36,11 @@ field bits<4> src1; field bits<4> src2; field bits<16> imm; - let Inst{31-28} = Opcode; - let Inst{27-24} = dest; - let Inst{23-20} = src1; - let Inst{19-16} = src2; - let Inst{15-0} = imm; + let Inst{31...28} = Opcode; + let Inst{27...24} = dest; + let Inst{23...20} = src1; + let Inst{19...16} = src2; + let Inst{15...0} = imm; } def AddRRI : RRI<"add", 0b0001>; @@ -83,7 +83,7 @@ // ADDINT-NEXT: OPC_CheckChild0Integer // ADDINT-NEXT: OPC_RecordChild1 // ADDINT-NEXT: OPC_RecordChild2 -// ADDINT-NEXT: OPC_EmitInteger, MVT::i32, 1 +// ADDINT-NEXT: OPC_EmitInteger, MVT::i32, 2 // ADDINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI) // SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB)