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comparison llvm/test/TableGen/DAGDefaultOps.td @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 1d019706d866
children
comparison
equal deleted inserted replaced
173:0572611fdcc8 207:2e18cbf3894f
14 class TestEncoding : Instruction { 14 class TestEncoding : Instruction {
15 field bits<32> Inst; 15 field bits<32> Inst;
16 } 16 }
17 17
18 class TestReg<int index> : Register<"R"#index, []> { 18 class TestReg<int index> : Register<"R"#index, []> {
19 let HWEncoding{15-4} = 0; 19 let HWEncoding{15...4} = 0;
20 let HWEncoding{3-0} = !cast<bits<4>>(index); 20 let HWEncoding{3...0} = !cast<bits<4>>(index);
21 } 21 }
22 foreach i = 0-15 in 22 foreach i = 0...15 in
23 def "R"#i : TestReg<i>; 23 def "R"#i : TestReg<i>;
24 24
25 def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 15)>; 25 def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 15)>;
26 26
27 def IntOperand: Operand<i32>; 27 def IntOperand: Operand<i32>;
34 string AsmVariantName = ""; 34 string AsmVariantName = "";
35 field bits<4> dest; 35 field bits<4> dest;
36 field bits<4> src1; 36 field bits<4> src1;
37 field bits<4> src2; 37 field bits<4> src2;
38 field bits<16> imm; 38 field bits<16> imm;
39 let Inst{31-28} = Opcode; 39 let Inst{31...28} = Opcode;
40 let Inst{27-24} = dest; 40 let Inst{27...24} = dest;
41 let Inst{23-20} = src1; 41 let Inst{23...20} = src1;
42 let Inst{19-16} = src2; 42 let Inst{19...16} = src2;
43 let Inst{15-0} = imm; 43 let Inst{15...0} = imm;
44 } 44 }
45 45
46 def AddRRI : RRI<"add", 0b0001>; 46 def AddRRI : RRI<"add", 0b0001>;
47 47
48 // I define one of these intrinsics with IntrNoMem and the other 48 // I define one of these intrinsics with IntrNoMem and the other
81 81
82 // ADDINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_WO_CHAIN) 82 // ADDINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_WO_CHAIN)
83 // ADDINT-NEXT: OPC_CheckChild0Integer 83 // ADDINT-NEXT: OPC_CheckChild0Integer
84 // ADDINT-NEXT: OPC_RecordChild1 84 // ADDINT-NEXT: OPC_RecordChild1
85 // ADDINT-NEXT: OPC_RecordChild2 85 // ADDINT-NEXT: OPC_RecordChild2
86 // ADDINT-NEXT: OPC_EmitInteger, MVT::i32, 1 86 // ADDINT-NEXT: OPC_EmitInteger, MVT::i32, 2
87 // ADDINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI) 87 // ADDINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI)
88 88
89 // SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB) 89 // SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB)
90 // SUB-NEXT: OPC_RecordChild0 90 // SUB-NEXT: OPC_RecordChild0
91 // SUB-NEXT: OPC_RecordChild1 91 // SUB-NEXT: OPC_RecordChild1