Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Mips/MipsCondMov.td @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
131 def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, 131 def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
132 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6; 132 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
133 133
134 let isCodeGenOnly = 1 in 134 let isCodeGenOnly = 1 in
135 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>, 135 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
136 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, 136 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
137 AdditionalRequires<[HasMips64]>;
138 137
139 def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>, 138 def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
140 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6; 139 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
141 140
142 let isCodeGenOnly = 1 in 141 let isCodeGenOnly = 1 in
143 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>, 142 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
144 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, 143 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
145 AdditionalRequires<[IsGP64bit]>;
146 144
147 def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, 145 def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
148 II_MOVZ_D>, CMov_I_F_FM<18, 17>, 146 II_MOVZ_D>, CMov_I_F_FM<18, 17>,
149 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 147 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
150 def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, 148 def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
167 def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>, 165 def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
168 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6; 166 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6;
169 167
170 let isCodeGenOnly = 1 in 168 let isCodeGenOnly = 1 in
171 def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>, 169 def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
172 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, 170 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
173 AdditionalRequires<[IsGP64bit]>;
174 171
175 def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>, 172 def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
176 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6; 173 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6;
177 174
178 let isCodeGenOnly = 1 in 175 let isCodeGenOnly = 1 in
179 def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>, 176 def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
180 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, 177 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
181 AdditionalRequires<[IsGP64bit]>;
182 178
183 def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>, 179 def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
184 CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6; 180 CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6;
185 def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>, 181 def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
186 CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6; 182 CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6;