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annotate lib/Target/Mips/MipsCondMov.td @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
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1 //===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This is the Conditional Moves implementation.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 // Conditional moves:
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15 // These instructions are expanded in
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16 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
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17 // conditional move instructions.
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18 // cond:int, data:int
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19 class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
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20 InstrItinClass Itin> :
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21 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
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22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
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23 let Constraints = "$F = $rd";
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24 }
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25
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26 // cond:int, data:float
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27 class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
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28 InstrItinClass Itin> :
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29 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
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30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>,
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31 HARDFLOAT {
0
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32 let Constraints = "$F = $fd";
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33 }
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34
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35 // cond:float, data:int
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36 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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37 SDPatternOperator OpNode = null_frag> :
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38 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
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39 !strconcat(opstr, "\t$rd, $rs, $fcc"),
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40 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
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41 Itin, FrmFR, opstr>, HARDFLOAT {
0
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42 let Constraints = "$F = $rd";
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43 }
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44
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45 // cond:float, data:float
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46 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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47 SDPatternOperator OpNode = null_frag> :
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48 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
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49 !strconcat(opstr, "\t$fd, $fs, $fcc"),
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50 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
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51 Itin, FrmFR, opstr>, HARDFLOAT {
0
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52 let Constraints = "$F = $fd";
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53 }
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54
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55 // select patterns
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56 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
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57 Instruction MOVZInst, Instruction SLTOp,
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58 Instruction SLTuOp, Instruction SLTiOp,
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59 Instruction SLTiuOp> {
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60 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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61 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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62 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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63 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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64 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
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65 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
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66 def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
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67 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
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68 def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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69 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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70 def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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71 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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72 def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
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73 DRC:$T, DRC:$F),
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74 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
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75 def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),
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76 DRC:$T, DRC:$F),
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77 (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
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78 DRC:$F)>;
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79 }
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80
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81 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
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82 Instruction MOVZInst, Instruction XOROp> {
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83 def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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84 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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85 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
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86 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
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87 }
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88
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89 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
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90 Instruction MOVZInst, Instruction XORiOp> {
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91 def : MipsPat<
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92 (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
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93 (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
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94 }
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95
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96 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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97 Instruction XOROp> {
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98 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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99 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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100 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
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101 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
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102 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
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103 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
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104 }
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105
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106 // Instantiation of instructions.
77
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107 def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
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108 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
0
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109
77
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110 let isCodeGenOnly = 1 in {
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111 def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
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112 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
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113 def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,
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114 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
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115 def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>,
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parents: 0
diff changeset
116 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
117 }
95c75e76d11b LLVM 3.4
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parents:
diff changeset
118
77
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parents: 0
diff changeset
119 def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
54457678186b LLVM 3.6
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parents: 0
diff changeset
120 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
121
77
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parents: 0
diff changeset
122 let isCodeGenOnly = 1 in {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
123 def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
124 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
54457678186b LLVM 3.6
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parents: 0
diff changeset
125 def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
54457678186b LLVM 3.6
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parents: 0
diff changeset
126 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
127 def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
128 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
129 }
95c75e76d11b LLVM 3.4
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parents:
diff changeset
130
77
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parents: 0
diff changeset
131 def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
132 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
133
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diff changeset
134 let isCodeGenOnly = 1 in
77
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parents: 0
diff changeset
135 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
120
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diff changeset
136 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
137
77
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parents: 0
diff changeset
138 def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
139 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
140
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parents:
diff changeset
141 let isCodeGenOnly = 1 in
77
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
142 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
120
1172e4bd9c6f update 4.0.0
mir3636
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diff changeset
143 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
0
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parents:
diff changeset
144
77
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parents: 0
diff changeset
145 def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
146 II_MOVZ_D>, CMov_I_F_FM<18, 17>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
147 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
148 def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
149 II_MOVN_D>, CMov_I_F_FM<19, 17>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
150 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
151
77
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diff changeset
152 let DecoderNamespace = "Mips64" in {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
153 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
154 CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
155 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
156 CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
157 let isCodeGenOnly = 1 in {
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
158 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
159 CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
160 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
161 CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
162 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 }
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parents:
diff changeset
164
77
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parents: 0
diff changeset
165 def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
166 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
167
95c75e76d11b LLVM 3.4
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parents:
diff changeset
168 let isCodeGenOnly = 1 in
77
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parents: 0
diff changeset
169 def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
120
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diff changeset
170 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
0
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parents:
diff changeset
171
77
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parents: 0
diff changeset
172 def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
173 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
174
95c75e76d11b LLVM 3.4
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parents:
diff changeset
175 let isCodeGenOnly = 1 in
77
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
176 def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
120
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diff changeset
177 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
0
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parents:
diff changeset
178
77
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parents: 0
diff changeset
179 def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
180 CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
181 def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
182 CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
183
77
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
184 def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
185 MipsCMovFP_T>, CMov_F_F_FM<17, 1>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
186 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
187 def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
188 MipsCMovFP_F>, CMov_F_F_FM<17, 0>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
189 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
190
77
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parents: 0
diff changeset
191 let DecoderNamespace = "Mips64" in {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
192 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
193 CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
194 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
195 CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
197
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parents:
diff changeset
198 // Instantiation of conditional move patterns.
77
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
200 INSN_MIPS4_32_NOT_32R6_64R6;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
201 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
202 defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
203
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
205 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
206 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
207 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
208 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
209 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
211 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
212 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
213 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
214 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
215 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
216 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
217 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
218 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
219 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
220 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
221 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
222
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
223 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
224
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
226 GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
227 defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
228 GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
229 defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
230 GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
231
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
233 INSN_MIPS4_32_NOT_32R6_64R6;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
234 defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
235 defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
236
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
237 defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
238 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
239 defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
240 GPR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
241 defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
242 GPR_64;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
243
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
245 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
246 defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
247 FGR_32;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
248 defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
249 FGR_32;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
250
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
252 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
253 defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
254 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
255 defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
256 FGR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
257 defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
258 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
259 defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
260 FGR_64;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
261 defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
262 FGR_64;
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
263
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
264 // For targets that don't have conditional-move instructions
60c9769439b8 LLVM 3.7
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diff changeset
265 // we have to match SELECT nodes with pseudo instructions.
60c9769439b8 LLVM 3.7
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diff changeset
266 let usesCustomInserter = 1 in {
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
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diff changeset
267 class Select_Pseudo<RegisterOperand RC> :
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268 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
269 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
270 ISA_MIPS1_NOT_4_32;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
271
60c9769439b8 LLVM 3.7
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parents: 77
diff changeset
272 class SelectFP_Pseudo_T<RegisterOperand RC> :
60c9769439b8 LLVM 3.7
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diff changeset
273 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
274 [(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>,
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
275 ISA_MIPS1_NOT_4_32;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
276
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
277 class SelectFP_Pseudo_F<RegisterOperand RC> :
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parents: 77
diff changeset
278 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
279 [(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>,
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
280 ISA_MIPS1_NOT_4_32;
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
281 }
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
282
60c9769439b8 LLVM 3.7
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parents: 77
diff changeset
283 def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>;
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parents: 77
diff changeset
284 def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>;
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parents: 77
diff changeset
285 def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>;
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parents: 77
diff changeset
286 def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32;
60c9769439b8 LLVM 3.7
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parents: 77
diff changeset
287 def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
288
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
289 def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
290 def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
291 def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
292 def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
293 def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
294
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
295 def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
296 def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>;
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
297 def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>;
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parents: 77
diff changeset
298 def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32;
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
299 def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64;