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comparison lib/Target/Mips/MipsInstrInfo.h @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
17 17
18 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 18 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
19 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 19 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
20 20
21 #include "Mips.h" 21 #include "Mips.h"
22 #include "MipsAnalyzeImmediate.h"
23 #include "MipsRegisterInfo.h" 22 #include "MipsRegisterInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetInstrInfo.h" 25 #include "llvm/Target/TargetInstrInfo.h"
27 26
49 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); 48 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
50 49
51 static const MipsInstrInfo *create(MipsSubtarget &STI); 50 static const MipsInstrInfo *create(MipsSubtarget &STI);
52 51
53 /// Branch Analysis 52 /// Branch Analysis
54 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 53 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
55 MachineBasicBlock *&FBB, 54 MachineBasicBlock *&FBB,
56 SmallVectorImpl<MachineOperand> &Cond, 55 SmallVectorImpl<MachineOperand> &Cond,
57 bool AllowModify) const override; 56 bool AllowModify) const override;
58 57
59 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 58 unsigned removeBranch(MachineBasicBlock &MBB,
59 int *BytesRemoved = nullptr) const override;
60 60
61 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 61 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
62 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 62 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
63 DebugLoc DL) const override; 63 const DebugLoc &DL,
64 int *BytesAdded = nullptr) const override;
64 65
65 bool 66 bool
66 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 67 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
67 68
68 BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 69 BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
69 MachineBasicBlock *&FBB, 70 MachineBasicBlock *&FBB,
70 SmallVectorImpl<MachineOperand> &Cond, 71 SmallVectorImpl<MachineOperand> &Cond,
71 bool AllowModify, 72 bool AllowModify,
72 SmallVectorImpl<MachineInstr*> &BranchInstrs) const; 73 SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
74
75 /// Determine the opcode of a non-delay slot form for a branch if one exists.
76 unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
77
78 /// Predicate to determine if an instruction can go in a forbidden slot.
79 bool SafeInForbiddenSlot(const MachineInstr &MI) const;
80
81 /// Predicate to determine if an instruction has a forbidden slot.
82 bool HasForbiddenSlot(const MachineInstr &MI) const;
73 83
74 /// Insert nop instruction when hazard condition is found 84 /// Insert nop instruction when hazard condition is found
75 void insertNoop(MachineBasicBlock &MBB, 85 void insertNoop(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator MI) const override; 86 MachineBasicBlock::iterator MI) const override;
77 87
82 virtual const MipsRegisterInfo &getRegisterInfo() const = 0; 92 virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
83 93
84 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; 94 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
85 95
86 /// Return the number of bytes of code the specified instruction may be. 96 /// Return the number of bytes of code the specified instruction may be.
87 unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 97 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
88 98
89 void storeRegToStackSlot(MachineBasicBlock &MBB, 99 void storeRegToStackSlot(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator MBBI, 100 MachineBasicBlock::iterator MBBI,
91 unsigned SrcReg, bool isKill, int FrameIndex, 101 unsigned SrcReg, bool isKill, int FrameIndex,
92 const TargetRegisterClass *RC, 102 const TargetRegisterClass *RC,
127 137
128 protected: 138 protected:
129 bool isZeroImm(const MachineOperand &op) const; 139 bool isZeroImm(const MachineOperand &op) const;
130 140
131 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, 141 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
132 unsigned Flag) const; 142 MachineMemOperand::Flags Flags) const;
133 143
134 private: 144 private:
135 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; 145 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
136 146
137 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 147 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
138 MachineBasicBlock *&BB, 148 MachineBasicBlock *&BB,
139 SmallVectorImpl<MachineOperand> &Cond) const; 149 SmallVectorImpl<MachineOperand> &Cond) const;
140 150
141 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL, 151 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
142 ArrayRef<MachineOperand> Cond) const; 152 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
143 }; 153 };
144 154
145 /// Create MipsInstrInfo objects. 155 /// Create MipsInstrInfo objects.
146 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); 156 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
147 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); 157 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);