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annotate lib/Target/Mips/MipsInstrInfo.h @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
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1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the Mips implementation of the TargetInstrInfo class.
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11 //
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12 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
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13 // order for MipsLongBranch pass to work correctly when the code has inline
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14 // assembly. The returned value doesn't have to be the asm instruction's exact
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15 // size in bytes; MipsLongBranch only expects it to be the correct upper bound.
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16 //===----------------------------------------------------------------------===//
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17
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18 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
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19 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
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20
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21 #include "Mips.h"
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22 #include "MipsRegisterInfo.h"
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23 #include "llvm/CodeGen/MachineInstrBuilder.h"
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24 #include "llvm/Support/ErrorHandling.h"
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25 #include "llvm/Target/TargetInstrInfo.h"
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26
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27 #define GET_INSTRINFO_HEADER
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28 #include "MipsGenInstrInfo.inc"
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29
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30 namespace llvm {
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31 class MipsSubtarget;
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32 class MipsInstrInfo : public MipsGenInstrInfo {
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33 virtual void anchor();
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34 protected:
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35 const MipsSubtarget &Subtarget;
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36 unsigned UncondBrOpc;
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37
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38 public:
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39 enum BranchType {
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40 BT_None, // Couldn't analyze branch.
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41 BT_NoBranch, // No branches found.
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42 BT_Uncond, // One unconditional branch.
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43 BT_Cond, // One conditional branch.
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44 BT_CondUncond, // A conditional branch followed by an unconditional branch.
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45 BT_Indirect // One indirct branch.
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46 };
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47
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48 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
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49
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50 static const MipsInstrInfo *create(MipsSubtarget &STI);
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51
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52 /// Branch Analysis
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53 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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54 MachineBasicBlock *&FBB,
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55 SmallVectorImpl<MachineOperand> &Cond,
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56 bool AllowModify) const override;
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57
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58 unsigned removeBranch(MachineBasicBlock &MBB,
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59 int *BytesRemoved = nullptr) const override;
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61 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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62 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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63 const DebugLoc &DL,
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64 int *BytesAdded = nullptr) const override;
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66 bool
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67 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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68
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69 BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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70 MachineBasicBlock *&FBB,
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71 SmallVectorImpl<MachineOperand> &Cond,
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72 bool AllowModify,
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73 SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
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74
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75 /// Determine the opcode of a non-delay slot form for a branch if one exists.
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76 unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
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77
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78 /// Predicate to determine if an instruction can go in a forbidden slot.
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79 bool SafeInForbiddenSlot(const MachineInstr &MI) const;
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80
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81 /// Predicate to determine if an instruction has a forbidden slot.
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82 bool HasForbiddenSlot(const MachineInstr &MI) const;
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83
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84 /// Insert nop instruction when hazard condition is found
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85 void insertNoop(MachineBasicBlock &MBB,
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86 MachineBasicBlock::iterator MI) const override;
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87
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88 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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89 /// such, whenever a client has an instance of instruction info, it should
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90 /// always be able to get register info as well (through this method).
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91 ///
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92 virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
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93
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94 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
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95
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96 /// Return the number of bytes of code the specified instruction may be.
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97 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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98
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99 void storeRegToStackSlot(MachineBasicBlock &MBB,
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100 MachineBasicBlock::iterator MBBI,
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101 unsigned SrcReg, bool isKill, int FrameIndex,
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102 const TargetRegisterClass *RC,
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103 const TargetRegisterInfo *TRI) const override {
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104 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
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105 }
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106
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107 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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108 MachineBasicBlock::iterator MBBI,
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109 unsigned DestReg, int FrameIndex,
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110 const TargetRegisterClass *RC,
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111 const TargetRegisterInfo *TRI) const override {
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112 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
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113 }
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114
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115 virtual void storeRegToStack(MachineBasicBlock &MBB,
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116 MachineBasicBlock::iterator MI,
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117 unsigned SrcReg, bool isKill, int FrameIndex,
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118 const TargetRegisterClass *RC,
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119 const TargetRegisterInfo *TRI,
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120 int64_t Offset) const = 0;
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121
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122 virtual void loadRegFromStack(MachineBasicBlock &MBB,
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123 MachineBasicBlock::iterator MI,
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124 unsigned DestReg, int FrameIndex,
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125 const TargetRegisterClass *RC,
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126 const TargetRegisterInfo *TRI,
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127 int64_t Offset) const = 0;
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128
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129 virtual void adjustStackPtr(unsigned SP, int64_t Amount,
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130 MachineBasicBlock &MBB,
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131 MachineBasicBlock::iterator I) const = 0;
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132
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133 /// Create an instruction which has the same operands and memory operands
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134 /// as MI but has a new opcode.
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135 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
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136 MachineBasicBlock::iterator I) const;
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137
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138 protected:
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139 bool isZeroImm(const MachineOperand &op) const;
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140
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141 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
120
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142 MachineMemOperand::Flags Flags) const;
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143
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144 private:
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145 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
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146
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147 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
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148 MachineBasicBlock *&BB,
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149 SmallVectorImpl<MachineOperand> &Cond) const;
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150
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151 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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152 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
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153 };
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154
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155 /// Create MipsInstrInfo objects.
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156 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
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157 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
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158
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159 }
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160
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161 #endif