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comparison lib/Target/Mips/MipsSubtarget.h @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
16 16
17 #include "MCTargetDesc/MipsABIInfo.h" 17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MipsFrameLowering.h" 18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h" 19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h" 20 #include "MipsInstrInfo.h"
21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
21 #include "llvm/IR/DataLayout.h" 22 #include "llvm/IR/DataLayout.h"
22 #include "llvm/MC/MCInstrItineraries.h" 23 #include "llvm/MC/MCInstrItineraries.h"
23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Target/TargetSelectionDAGInfo.h"
25 #include "llvm/Target/TargetSubtargetInfo.h" 25 #include "llvm/Target/TargetSubtargetInfo.h"
26 #include <string> 26 #include <string>
27 27
28 #define GET_SUBTARGETINFO_HEADER 28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc" 29 #include "MipsGenSubtargetInfo.inc"
79 bool IsNaN2008bit; 79 bool IsNaN2008bit;
80 80
81 // IsFP64bit - General-purpose registers are 64 bits wide 81 // IsFP64bit - General-purpose registers are 64 bits wide
82 bool IsGP64bit; 82 bool IsGP64bit;
83 83
84 // IsPTR64bit - Pointers are 64 bit wide
85 bool IsPTR64bit;
86
84 // HasVFPU - Processor has a vector floating point unit. 87 // HasVFPU - Processor has a vector floating point unit.
85 bool HasVFPU; 88 bool HasVFPU;
86 89
87 // CPU supports cnMIPS (Cavium Networks Octeon CPU). 90 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
88 bool HasCnMips; 91 bool HasCnMips;
150 153
151 const MipsTargetMachine &TM; 154 const MipsTargetMachine &TM;
152 155
153 Triple TargetTriple; 156 Triple TargetTriple;
154 157
155 const TargetSelectionDAGInfo TSInfo; 158 const SelectionDAGTargetInfo TSInfo;
156 std::unique_ptr<const MipsInstrInfo> InstrInfo; 159 std::unique_ptr<const MipsInstrInfo> InstrInfo;
157 std::unique_ptr<const MipsFrameLowering> FrameLowering; 160 std::unique_ptr<const MipsFrameLowering> FrameLowering;
158 std::unique_ptr<const MipsTargetLowering> TLInfo; 161 std::unique_ptr<const MipsTargetLowering> TLInfo;
159 162
160 public: 163 public:
164 bool isPositionIndependent() const;
161 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. 165 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
162 bool enablePostRAScheduler() const override; 166 bool enablePostRAScheduler() const override;
163 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; 167 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
164 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; 168 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
165 169
166 /// Only O32 and EABI supported right now.
167 bool isABI_EABI() const;
168 bool isABI_N64() const; 170 bool isABI_N64() const;
169 bool isABI_N32() const; 171 bool isABI_N32() const;
170 bool isABI_O32() const; 172 bool isABI_O32() const;
171 const MipsABIInfo &getABI() const; 173 const MipsABIInfo &getABI() const;
172 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } 174 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
223 bool noOddSPReg() const { return !UseOddSPReg; } 225 bool noOddSPReg() const { return !UseOddSPReg; }
224 bool isNaN2008() const { return IsNaN2008bit; } 226 bool isNaN2008() const { return IsNaN2008bit; }
225 bool isGP64bit() const { return IsGP64bit; } 227 bool isGP64bit() const { return IsGP64bit; }
226 bool isGP32bit() const { return !IsGP64bit; } 228 bool isGP32bit() const { return !IsGP64bit; }
227 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; } 229 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
230 bool isPTR64bit() const { return IsPTR64bit; }
231 bool isPTR32bit() const { return !IsPTR64bit; }
228 bool isSingleFloat() const { return IsSingleFloat; } 232 bool isSingleFloat() const { return IsSingleFloat; }
229 bool hasVFPU() const { return HasVFPU; } 233 bool hasVFPU() const { return HasVFPU; }
230 bool inMips16Mode() const { return InMips16Mode; } 234 bool inMips16Mode() const { return InMips16Mode; }
231 bool inMips16ModeDefault() const { 235 bool inMips16ModeDefault() const {
232 return InMips16Mode; 236 return InMips16Mode;
288 292
289 // Set helper classes 293 // Set helper classes
290 void setHelperClassesMips16(); 294 void setHelperClassesMips16();
291 void setHelperClassesMipsSE(); 295 void setHelperClassesMipsSE();
292 296
293 const TargetSelectionDAGInfo *getSelectionDAGInfo() const override { 297 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
294 return &TSInfo; 298 return &TSInfo;
295 } 299 }
296 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } 300 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
297 const TargetFrameLowering *getFrameLowering() const override { 301 const TargetFrameLowering *getFrameLowering() const override {
298 return FrameLowering.get(); 302 return FrameLowering.get();