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1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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77
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14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
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|
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15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
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16
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83
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17 #include "MCTargetDesc/MipsABIInfo.h"
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77
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18 #include "MipsFrameLowering.h"
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|
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19 #include "MipsISelLowering.h"
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20 #include "MipsInstrInfo.h"
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120
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21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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77
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22 #include "llvm/IR/DataLayout.h"
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23 #include "llvm/MC/MCInstrItineraries.h"
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24 #include "llvm/Support/ErrorHandling.h"
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25 #include "llvm/Target/TargetSubtargetInfo.h"
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26 #include <string>
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27
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28 #define GET_SUBTARGETINFO_HEADER
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29 #include "MipsGenSubtargetInfo.inc"
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30
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31 namespace llvm {
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32 class StringRef;
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33
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34 class MipsTargetMachine;
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35
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36 class MipsSubtarget : public MipsGenSubtargetInfo {
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37 virtual void anchor();
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38
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39 enum MipsArchEnum {
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40 MipsDefault,
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41 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
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42 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
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43 };
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44
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45 enum class CPU { P5600 };
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46
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47 // Mips architecture version
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48 MipsArchEnum MipsArchVersion;
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49
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50 // Processor implementation (unused but required to exist by
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51 // tablegen-erated code).
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52 CPU ProcImpl;
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53
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54 // IsLittle - The target is Little Endian
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55 bool IsLittle;
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56
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57 // IsSoftFloat - The target does not support any floating point instructions.
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58 bool IsSoftFloat;
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59
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60 // IsSingleFloat - The target only supports single precision float
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61 // point operations. This enable the target to use all 32 32-bit
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62 // floating point registers instead of only using even ones.
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63 bool IsSingleFloat;
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64
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65 // IsFPXX - MIPS O32 modeless ABI.
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66 bool IsFPXX;
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67
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68 // NoABICalls - Disable SVR4-style position-independent code.
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69 bool NoABICalls;
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70
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71 // IsFP64bit - The target processor has 64-bit floating point registers.
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72 bool IsFP64bit;
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73
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77
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74 /// Are odd single-precision registers permitted?
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75 /// This corresponds to -modd-spreg and -mno-odd-spreg
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76 bool UseOddSPReg;
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77
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78 // IsNan2008 - IEEE 754-2008 NaN encoding.
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79 bool IsNaN2008bit;
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80
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81 // IsFP64bit - General-purpose registers are 64 bits wide
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82 bool IsGP64bit;
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83
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120
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84 // IsPTR64bit - Pointers are 64 bit wide
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85 bool IsPTR64bit;
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86
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87 // HasVFPU - Processor has a vector floating point unit.
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88 bool HasVFPU;
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89
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90 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
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91 bool HasCnMips;
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92
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93 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
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94 bool IsLinux;
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95
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96 // UseSmallSection - Small section is used.
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97 bool UseSmallSection;
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98
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99 /// Features related to the presence of specific instructions.
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100
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101 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
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102 bool HasMips3_32;
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103
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104 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
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105 bool HasMips3_32r2;
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106
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107 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
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108 bool HasMips4_32;
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109
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110 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
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111 bool HasMips4_32r2;
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112
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113 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
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114 bool HasMips5_32r2;
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115
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116 // InMips16 -- can process Mips16 instructions
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117 bool InMips16Mode;
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118
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119 // Mips16 hard float
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120 bool InMips16HardFloat;
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121
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122 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
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123 bool PreviousInMips16Mode;
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124
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125 // InMicroMips -- can process MicroMips instructions
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126 bool InMicroMipsMode;
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127
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128 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
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129 bool HasDSP, HasDSPR2, HasDSPR3;
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130
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131 // Allow mixed Mips16 and Mips32 in one source file
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132 bool AllowMixed16_32;
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133
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134 // Optimize for space by compiling all functions as Mips 16 unless
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135 // it needs floating point. Functions needing floating point are
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136 // compiled as Mips32
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137 bool Os16;
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138
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139 // HasMSA -- supports MSA ASE.
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140 bool HasMSA;
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141
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95
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142 // UseTCCInDIV -- Enables the use of trapping in the assembler.
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143 bool UseTCCInDIV;
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144
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145 // HasEVA -- supports EVA ASE.
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146 bool HasEVA;
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147
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148 InstrItineraryData InstrItins;
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149
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150 // We can override the determination of whether we are in mips16 mode
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151 // as from the command line
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152 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
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153
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83
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154 const MipsTargetMachine &TM;
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155
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77
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156 Triple TargetTriple;
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|
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157
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120
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158 const SelectionDAGTargetInfo TSInfo;
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77
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159 std::unique_ptr<const MipsInstrInfo> InstrInfo;
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|
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160 std::unique_ptr<const MipsFrameLowering> FrameLowering;
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|
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161 std::unique_ptr<const MipsTargetLowering> TLInfo;
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162
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163 public:
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120
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164 bool isPositionIndependent() const;
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77
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165 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
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95
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166 bool enablePostRAScheduler() const override;
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77
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167 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
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168 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
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169
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83
|
170 bool isABI_N64() const;
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171 bool isABI_N32() const;
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172 bool isABI_O32() const;
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173 const MipsABIInfo &getABI() const;
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77
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174 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
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175
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176 /// This constructor initializes the data members to match that
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177 /// of the specified triple.
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95
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178 MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
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179 bool little, const MipsTargetMachine &TM);
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180
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181 /// ParseSubtargetFeatures - Parses features string setting specified
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182 /// subtarget options. Definition of function is auto generated by tblgen.
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183 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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184
|
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77
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185 bool hasMips1() const { return MipsArchVersion >= Mips1; }
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|
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186 bool hasMips2() const { return MipsArchVersion >= Mips2; }
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187 bool hasMips3() const { return MipsArchVersion >= Mips3; }
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188 bool hasMips4() const { return MipsArchVersion >= Mips4; }
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189 bool hasMips5() const { return MipsArchVersion >= Mips5; }
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190 bool hasMips4_32() const { return HasMips4_32; }
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191 bool hasMips4_32r2() const { return HasMips4_32r2; }
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|
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192 bool hasMips32() const {
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83
|
193 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
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|
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194 hasMips64();
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|
77
|
195 }
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|
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196 bool hasMips32r2() const {
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83
|
197 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
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198 hasMips64r2();
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77
|
199 }
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95
|
200 bool hasMips32r3() const {
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|
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201 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
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|
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202 hasMips64r2();
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|
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203 }
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204 bool hasMips32r5() const {
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205 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
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206 hasMips64r5();
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|
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207 }
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77
|
208 bool hasMips32r6() const {
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83
|
209 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
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210 hasMips64r6();
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211 }
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212 bool hasMips64() const { return MipsArchVersion >= Mips64; }
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83
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213 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
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214 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
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215 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
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216 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
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217
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218 bool hasCnMips() const { return HasCnMips; }
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219
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220 bool isLittle() const { return IsLittle; }
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77
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221 bool isABICalls() const { return !NoABICalls; }
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222 bool isFPXX() const { return IsFPXX; }
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223 bool isFP64bit() const { return IsFP64bit; }
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77
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224 bool useOddSPReg() const { return UseOddSPReg; }
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225 bool noOddSPReg() const { return !UseOddSPReg; }
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226 bool isNaN2008() const { return IsNaN2008bit; }
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227 bool isGP64bit() const { return IsGP64bit; }
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228 bool isGP32bit() const { return !IsGP64bit; }
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229 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
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120
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230 bool isPTR64bit() const { return IsPTR64bit; }
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231 bool isPTR32bit() const { return !IsPTR64bit; }
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232 bool isSingleFloat() const { return IsSingleFloat; }
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233 bool hasVFPU() const { return HasVFPU; }
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234 bool inMips16Mode() const { return InMips16Mode; }
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235 bool inMips16ModeDefault() const {
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236 return InMips16Mode;
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237 }
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238 // Hard float for mips16 means essentially to compile as soft float
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239 // but to use a runtime library for soft float that is written with
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240 // native mips32 floating point instructions (those runtime routines
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241 // run in mips32 hard float mode).
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242 bool inMips16HardFloat() const {
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243 return inMips16Mode() && InMips16HardFloat;
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244 }
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245 bool inMicroMipsMode() const { return InMicroMipsMode; }
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246 bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
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247 bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
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248 bool hasDSP() const { return HasDSP; }
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249 bool hasDSPR2() const { return HasDSPR2; }
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250 bool hasDSPR3() const { return HasDSPR3; }
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251 bool hasMSA() const { return HasMSA; }
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252 bool hasEVA() const { return HasEVA; }
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253 bool useSmallSection() const { return UseSmallSection; }
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254
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255 bool hasStandardEncoding() const { return !inMips16Mode(); }
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256
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257 bool useSoftFloat() const { return IsSoftFloat; }
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258
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259 bool enableLongBranchPass() const {
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260 return hasStandardEncoding() || allowMixed16_32();
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261 }
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262
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263 /// Features related to the presence of specific instructions.
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264 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
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265 bool hasMTHC1() const { return hasMips32r2(); }
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266
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267 bool allowMixed16_32() const { return inMips16ModeDefault() |
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268 AllowMixed16_32; }
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269
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270 bool os16() const { return Os16; }
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271
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272 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
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273
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274 // for now constant islands are on for the whole compilation unit but we only
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275 // really use them if in addition we are in mips16 mode
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276 static bool useConstantIslands();
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277
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278 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
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279
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280 // Grab relocation model
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281 Reloc::Model getRelocationModel() const;
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282
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283 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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284 const TargetMachine &TM);
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285
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286 /// Does the system support unaligned memory access.
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287 ///
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288 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
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289 /// specify which component of the system provides it. Hardware, software, and
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290 /// hybrid implementations are all valid.
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291 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
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292
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293 // Set helper classes
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294 void setHelperClassesMips16();
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295 void setHelperClassesMipsSE();
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296
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297 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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298 return &TSInfo;
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299 }
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300 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
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301 const TargetFrameLowering *getFrameLowering() const override {
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302 return FrameLowering.get();
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303 }
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304 const MipsRegisterInfo *getRegisterInfo() const override {
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305 return &InstrInfo->getRegisterInfo();
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306 }
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307 const MipsTargetLowering *getTargetLowering() const override {
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308 return TLInfo.get();
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309 }
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310 const InstrItineraryData *getInstrItineraryData() const override {
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311 return &InstrItins;
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312 }
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313 };
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314 } // End llvm namespace
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315
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316 #endif
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