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comparison lib/Target/SystemZ/SystemZScheduleZEC12.td @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
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101:34baf5011add 120:1172e4bd9c6f
1 //=- SystemZScheduleZEC12.td - SystemZ Scheduling Definitions --*- tblgen -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the machine model for ZEC12 to support instruction
11 // scheduling and other instruction cost heuristics.
12 //
13 //===----------------------------------------------------------------------===//
14
15 def ZEC12Model : SchedMachineModel {
16
17 let UnsupportedFeatures = Arch10UnsupportedFeatures.List;
18
19 let IssueWidth = 5;
20 let MicroOpBufferSize = 40; // Issue queues
21 let LoadLatency = 1; // Optimistic load latency.
22
23 let PostRAScheduler = 1;
24
25 // Extra cycles for a mispredicted branch.
26 let MispredictPenalty = 8;
27 }
28
29 let SchedModel = ZEC12Model in {
30
31 // These definitions could be put in a subtarget common include file,
32 // but it seems the include system in Tablegen currently rejects
33 // multiple includes of same file.
34 def : WriteRes<GroupAlone, []> {
35 let NumMicroOps = 0;
36 let BeginGroup = 1;
37 let EndGroup = 1;
38 }
39 def : WriteRes<EndGroup, []> {
40 let NumMicroOps = 0;
41 let EndGroup = 1;
42 }
43 def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
44 def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
45 def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
46 def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
47 def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
48 def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
49 def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
50 def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
51 def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
52 def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
53 def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
54 def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
55 def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
56 def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
57
58 // Execution units.
59 def ZEC12_FXUnit : ProcResource<2>;
60 def ZEC12_LSUnit : ProcResource<2>;
61 def ZEC12_FPUnit : ProcResource<1>;
62 def ZEC12_VBUnit : ProcResource<1>;
63
64 // Subtarget specific definitions of scheduling resources.
65 def : WriteRes<FXU, [ZEC12_FXUnit]> { let Latency = 1; }
66 def : WriteRes<LSU, [ZEC12_LSUnit]> { let Latency = 4; }
67 def : WriteRes<LSU_lat1, [ZEC12_LSUnit]> { let Latency = 1; }
68 def : WriteRes<FPU, [ZEC12_FPUnit]> { let Latency = 8; }
69 def : WriteRes<FPU2, [ZEC12_FPUnit, ZEC12_FPUnit]> { let Latency = 9; }
70 def : WriteRes<VBU, [ZEC12_VBUnit]>; // Virtual Branching Unit
71
72 // -------------------------- INSTRUCTIONS ---------------------------------- //
73
74 // InstRW constructs have been used in order to preserve the
75 // readability of the InstrInfo files.
76
77 // For each instruction, as matched by a regexp, provide a list of
78 // resources that it needs. These will be combined into a SchedClass.
79
80 //===----------------------------------------------------------------------===//
81 // Stack allocation
82 //===----------------------------------------------------------------------===//
83
84 def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
85
86 //===----------------------------------------------------------------------===//
87 // Branch instructions
88 //===----------------------------------------------------------------------===//
89
90 // Branch
91 def : InstRW<[VBU], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
92 def : InstRW<[VBU], (instregex "(Call)?J(G)?(Asm.*)?$")>;
93 def : InstRW<[LSU, Lat4], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
94 def : InstRW<[LSU, Lat4], (instregex "(Call)?B(R)?(Asm.*)?$")>;
95 def : InstRW<[FXU, EndGroup], (instregex "BRCT(G)?$")>;
96 def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone], (instregex "BRX(H|LE)$")>;
97
98 // Compare and branch
99 def : InstRW<[FXU], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
100 def : InstRW<[FXU, LSU, Lat5, GroupAlone],
101 (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
102
103 //===----------------------------------------------------------------------===//
104 // Trap instructions
105 //===----------------------------------------------------------------------===//
106
107 // Trap
108 def : InstRW<[VBU], (instregex "(Cond)?Trap$")>;
109
110 // Compare and trap
111 def : InstRW<[FXU], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
112 def : InstRW<[FXU], (instregex "CL(G)?RT(Asm.*)?$")>;
113 def : InstRW<[FXU], (instregex "CL(F|G)IT(Asm.*)?$")>;
114 def : InstRW<[FXU, LSU, Lat5], (instregex "CL(G)?T(Asm.*)?$")>;
115
116 //===----------------------------------------------------------------------===//
117 // Call and return instructions
118 //===----------------------------------------------------------------------===//
119
120 // Call
121 def : InstRW<[VBU, FXU, FXU, Lat3, GroupAlone], (instregex "(Call)?BRAS$")>;
122 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
123 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
124 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
125
126 // Return
127 def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
128 def : InstRW<[LSU_lat1], (instregex "CondReturn$")>;
129
130 //===----------------------------------------------------------------------===//
131 // Select instructions
132 //===----------------------------------------------------------------------===//
133
134 // Select pseudo
135 def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
136
137 // CondStore pseudos
138 def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
139 def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
140 def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
141 def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
142 def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
143 def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
144
145 //===----------------------------------------------------------------------===//
146 // Move instructions
147 //===----------------------------------------------------------------------===//
148
149 // Moves
150 def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
151 def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
152
153 // Move character
154 def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
155
156 // Pseudo -> reg move
157 def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
158 def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
159 def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
160 def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
161 def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
162
163 // Loads
164 def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
165 def : InstRW<[LSU], (instregex "LG(RL)?$")>;
166 def : InstRW<[LSU], (instregex "L128$")>;
167
168 def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
169 def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
170
171 def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
172 def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
173 def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
174
175 // Load and test
176 def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
177 def : InstRW<[FXU], (instregex "LT(G)?R$")>;
178
179 // Stores
180 def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
181 def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
182 def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
183
184 // String moves.
185 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
186
187 //===----------------------------------------------------------------------===//
188 // Conditional move instructions
189 //===----------------------------------------------------------------------===//
190
191 def : InstRW<[FXU, Lat2], (instregex "LOC(G)?R(Asm.*)?$")>;
192 def : InstRW<[FXU, Lat2], (instregex "LOC(G)?HI(Asm.*)?$")>;
193 def : InstRW<[FXU, LSU, Lat6], (instregex "LOC(G)?(Asm.*)?$")>;
194 def : InstRW<[FXU, LSU, Lat5], (instregex "STOC(G)?(Asm.*)?$")>;
195
196 //===----------------------------------------------------------------------===//
197 // Sign extensions
198 //===----------------------------------------------------------------------===//
199
200 def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
201 def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
202
203 def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
204 def : InstRW<[FXU], (instregex "LTGFR$")>;
205
206 def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
207 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
208 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
209 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
210 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
211
212 //===----------------------------------------------------------------------===//
213 // Zero extensions
214 //===----------------------------------------------------------------------===//
215
216 def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
217 def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
218 def : InstRW<[FXU], (instregex "LLG(C|H|F|T)R$")>;
219 def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
220 def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
221 def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
222 def : InstRW<[LSU], (instregex "LLHRL$")>;
223 def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
224
225 //===----------------------------------------------------------------------===//
226 // Truncations
227 //===----------------------------------------------------------------------===//
228
229 def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
230 def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
231
232 //===----------------------------------------------------------------------===//
233 // Multi-register moves
234 //===----------------------------------------------------------------------===//
235
236 // Load multiple (estimated average of 5 ops)
237 def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
238 (instregex "LM(H|Y|G)?$")>;
239
240 // Store multiple (estimated average of 3 ops)
241 def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
242 (instregex "STM(H|Y|G)?$")>;
243
244 //===----------------------------------------------------------------------===//
245 // Byte swaps
246 //===----------------------------------------------------------------------===//
247
248 def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
249 def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
250 def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
251
252 //===----------------------------------------------------------------------===//
253 // Load address instructions
254 //===----------------------------------------------------------------------===//
255
256 def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
257
258 // Load the Global Offset Table address
259 def : InstRW<[FXU], (instregex "GOT$")>;
260
261 //===----------------------------------------------------------------------===//
262 // Absolute and Negation
263 //===----------------------------------------------------------------------===//
264
265 def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
266 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
267 def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
268 def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
269 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
270
271 //===----------------------------------------------------------------------===//
272 // Insertion
273 //===----------------------------------------------------------------------===//
274
275 def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
276 def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
277 def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
278 def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
279 def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
280 def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
281 def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
282 def : InstRW<[FXU], (instregex "IILF(64)?$")>;
283 def : InstRW<[FXU], (instregex "IILH(64)?$")>;
284 def : InstRW<[FXU], (instregex "IILL(64)?$")>;
285
286 //===----------------------------------------------------------------------===//
287 // Addition
288 //===----------------------------------------------------------------------===//
289
290 def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
291 def : InstRW<[FXU, LSU, Lat6], (instregex "AH(Y)?$")>;
292 def : InstRW<[FXU], (instregex "AIH$")>;
293 def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
294 def : InstRW<[FXU], (instregex "AGFI$")>;
295 def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
296 def : InstRW<[FXU], (instregex "AGR(K)?$")>;
297 def : InstRW<[FXU], (instregex "AHI(K)?$")>;
298 def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
299 def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
300 def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
301 def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
302 def : InstRW<[FXU], (instregex "ALGHSIK$")>;
303 def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
304 def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
305 def : InstRW<[FXU], (instregex "ALR(K)?$")>;
306 def : InstRW<[FXU], (instregex "AR(K)?$")>;
307 def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
308
309 // Logical addition with carry
310 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
311 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
312
313 // Add with sign extension (32 -> 64)
314 def : InstRW<[FXU, LSU, Lat6], (instregex "AGF$")>;
315 def : InstRW<[FXU, Lat2], (instregex "AGFR$")>;
316
317 //===----------------------------------------------------------------------===//
318 // Subtraction
319 //===----------------------------------------------------------------------===//
320
321 def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
322 def : InstRW<[FXU, LSU, Lat6], (instregex "SH(Y)?$")>;
323 def : InstRW<[FXU], (instregex "SGR(K)?$")>;
324 def : InstRW<[FXU], (instregex "SLFI$")>;
325 def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
326 def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
327 def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
328 def : InstRW<[FXU], (instregex "SLR(K)?$")>;
329 def : InstRW<[FXU], (instregex "SR(K)?$")>;
330
331 // Subtraction with borrow
332 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
333 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
334
335 // Subtraction with sign extension (32 -> 64)
336 def : InstRW<[FXU, LSU, Lat6], (instregex "SGF$")>;
337 def : InstRW<[FXU, Lat2], (instregex "SGFR$")>;
338
339 //===----------------------------------------------------------------------===//
340 // AND
341 //===----------------------------------------------------------------------===//
342
343 def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
344 def : InstRW<[FXU], (instregex "NGR(K)?$")>;
345 def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
346 def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
347 def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
348 def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
349 def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
350 def : InstRW<[FXU], (instregex "NILF(64)?$")>;
351 def : InstRW<[FXU], (instregex "NILH(64)?$")>;
352 def : InstRW<[FXU], (instregex "NILL(64)?$")>;
353 def : InstRW<[FXU], (instregex "NR(K)?$")>;
354 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
355
356 //===----------------------------------------------------------------------===//
357 // OR
358 //===----------------------------------------------------------------------===//
359
360 def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
361 def : InstRW<[FXU], (instregex "OGR(K)?$")>;
362 def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
363 def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
364 def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
365 def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
366 def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
367 def : InstRW<[FXU], (instregex "OILF(64)?$")>;
368 def : InstRW<[FXU], (instregex "OILH(64)?$")>;
369 def : InstRW<[FXU], (instregex "OILL(64)?$")>;
370 def : InstRW<[FXU], (instregex "OR(K)?$")>;
371 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
372
373 //===----------------------------------------------------------------------===//
374 // XOR
375 //===----------------------------------------------------------------------===//
376
377 def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
378 def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
379 def : InstRW<[FXU], (instregex "XIFMux$")>;
380 def : InstRW<[FXU], (instregex "XGR(K)?$")>;
381 def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
382 def : InstRW<[FXU], (instregex "XILF(64)?$")>;
383 def : InstRW<[FXU], (instregex "XR(K)?$")>;
384 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
385
386 //===----------------------------------------------------------------------===//
387 // Multiplication
388 //===----------------------------------------------------------------------===//
389
390 def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
391 def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
392 def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
393 def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
394 def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
395 def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
396 def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
397 def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
398 def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
399 def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
400
401 //===----------------------------------------------------------------------===//
402 // Division and remainder
403 //===----------------------------------------------------------------------===//
404
405 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
406 (instregex "DSG(F)?R$")>;
407 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
408 (instregex "DSG(F)?$")>;
409 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
410 (instregex "DL(G)?R$")>;
411 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
412 (instregex "DL(G)?$")>;
413
414 //===----------------------------------------------------------------------===//
415 // Shifts
416 //===----------------------------------------------------------------------===//
417
418 def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
419 def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
420 def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
421 def : InstRW<[FXU], (instregex "SLA(K)?$")>;
422
423 // Rotate
424 def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
425
426 // Rotate and insert
427 def : InstRW<[FXU], (instregex "RISBG(N|32)?$")>;
428 def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
429 def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
430 def : InstRW<[FXU], (instregex "RISBMux$")>;
431
432 // Rotate and Select
433 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
434
435 //===----------------------------------------------------------------------===//
436 // Comparison
437 //===----------------------------------------------------------------------===//
438
439 def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
440 def : InstRW<[FXU], (instregex "CFI(Mux)?$")>;
441 def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
442 def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
443 def : InstRW<[FXU], (instregex "C(G)?R$")>;
444 def : InstRW<[FXU], (instregex "C(HI|IH)$")>;
445 def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
446 def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
447 def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
448 def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
449 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
450 def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
451 def : InstRW<[FXU], (instregex "CLGR$")>;
452 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
453 def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
454 def : InstRW<[FXU], (instregex "CLIH$")>;
455 def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
456 def : InstRW<[FXU], (instregex "CLR$")>;
457 def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
458
459 // Compare halfword
460 def : InstRW<[FXU, LSU, Lat6], (instregex "CH(Y|RL)?$")>;
461 def : InstRW<[FXU, LSU, Lat6], (instregex "CGH(RL)?$")>;
462 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CHHSI$")>;
463
464 // Compare with sign extension (32 -> 64)
465 def : InstRW<[FXU, LSU, Lat6], (instregex "CGF(RL)?$")>;
466 def : InstRW<[FXU, Lat2], (instregex "CGFR$")>;
467
468 // Compare logical character
469 def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "CLC$")>;
470
471 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
472
473 // Test under mask
474 def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
475 def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
476 def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
477 def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
478 def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
479 def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
480
481 //===----------------------------------------------------------------------===//
482 // Prefetch
483 //===----------------------------------------------------------------------===//
484
485 def : InstRW<[LSU], (instregex "PFD(RL)?$")>;
486
487 //===----------------------------------------------------------------------===//
488 // Atomic operations
489 //===----------------------------------------------------------------------===//
490
491 def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
492
493 def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
494 def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
495 def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
496 def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
497 def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
498
499 // Compare and swap
500 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
501
502 //===----------------------------------------------------------------------===//
503 // Access registers
504 //===----------------------------------------------------------------------===//
505
506 // Extract/set/copy access register
507 def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
508
509 // Load address extended
510 def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
511
512 // Load/store access multiple (not modeled precisely)
513 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
514
515 //===----------------------------------------------------------------------===//
516 // Program mask and addressing mode
517 //===----------------------------------------------------------------------===//
518
519 // Insert Program Mask
520 def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
521
522 // Set Program Mask
523 def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
524
525 // Branch and link
526 def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
527
528 // Test addressing mode
529 def : InstRW<[FXU], (instregex "TAM$")>;
530
531 // Set addressing mode
532 def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
533
534 // Branch (and save) and set mode.
535 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
536 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
537
538 //===----------------------------------------------------------------------===//
539 // Transactional execution
540 //===----------------------------------------------------------------------===//
541
542 // Transaction begin
543 def : InstRW<[LSU, LSU, FXU, FXU, FXU, FXU, FXU, Lat15, GroupAlone],
544 (instregex "TBEGIN(C|_nofloat)?$")>;
545
546 // Transaction end
547 def : InstRW<[LSU, GroupAlone], (instregex "TEND$")>;
548
549 // Transaction abort
550 def : InstRW<[LSU, GroupAlone], (instregex "TABORT$")>;
551
552 // Extract Transaction Nesting Depth
553 def : InstRW<[FXU], (instregex "ETND$")>;
554
555 // Nontransactional store
556 def : InstRW<[FXU, LSU, Lat5], (instregex "NTSTG$")>;
557
558 //===----------------------------------------------------------------------===//
559 // Processor assist
560 //===----------------------------------------------------------------------===//
561
562 def : InstRW<[FXU], (instregex "PPA$")>;
563
564 //===----------------------------------------------------------------------===//
565 // Miscellaneous Instructions.
566 //===----------------------------------------------------------------------===//
567
568 // Find leftmost one
569 def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
570
571 // Population count
572 def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
573
574 // Extend
575 def : InstRW<[FXU], (instregex "AEXT128_64$")>;
576 def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
577
578 // String instructions
579 def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
580
581 // Move with key
582 def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
583
584 // Extract CPU Time
585 def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
586
587 // Execute
588 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
589
590 // Program return
591 def : InstRW<[FXU, Lat30], (instregex "PR$")>;
592
593 // Inline assembly
594 def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "STCK(F)?$")>;
595 def : InstRW<[LSU, LSU, LSU, LSU, FXU, FXU, Lat20, GroupAlone],
596 (instregex "STCKE$")>;
597 def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
598 def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
599
600 // Store real address
601 def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
602
603 //===----------------------------------------------------------------------===//
604 // .insn directive instructions
605 //===----------------------------------------------------------------------===//
606
607 // An "empty" sched-class will be assigned instead of the "invalid sched-class".
608 // getNumDecoderSlots() will then return 1 instead of 0.
609 def : InstRW<[], (instregex "Insn.*")>;
610
611
612 // ----------------------------- Floating point ----------------------------- //
613
614 //===----------------------------------------------------------------------===//
615 // FP: Select instructions
616 //===----------------------------------------------------------------------===//
617
618 def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
619 def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
620 def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
621
622 //===----------------------------------------------------------------------===//
623 // FP: Move instructions
624 //===----------------------------------------------------------------------===//
625
626 // Load zero
627 def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
628 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
629
630 // Load
631 def : InstRW<[FXU], (instregex "LER$")>;
632 def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
633 def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
634 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
635
636 // Load and Test
637 def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
638 def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
639 def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
640 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
641 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
642 (instregex "LTXBRCompare(_VecPseudo)?$")>;
643
644 // Copy sign
645 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
646 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
647
648 //===----------------------------------------------------------------------===//
649 // FP: Load instructions
650 //===----------------------------------------------------------------------===//
651
652 def : InstRW<[LSU], (instregex "LE(Y)?$")>;
653 def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
654 def : InstRW<[LSU], (instregex "LX$")>;
655
656 //===----------------------------------------------------------------------===//
657 // FP: Store instructions
658 //===----------------------------------------------------------------------===//
659
660 def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
661 def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
662 def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
663
664 //===----------------------------------------------------------------------===//
665 // FP: Conversion instructions
666 //===----------------------------------------------------------------------===//
667
668 // Load rounded
669 def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
670 def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
671 def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
672
673 // Load lengthened
674 def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
675 def : InstRW<[FPU], (instregex "LDEBR$")>;
676 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
677 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
678
679 // Convert from fixed / logical
680 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A?)$")>;
681 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A?)$")>;
682 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A?)$")>;
683 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
684 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
685 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
686
687 // Convert to fixed / logical
688 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A?)$")>;
689 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A?)$")>;
690 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A?)$")>;
691 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
692 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
693 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
694
695 //===----------------------------------------------------------------------===//
696 // FP: Unary arithmetic
697 //===----------------------------------------------------------------------===//
698
699 // Load Complement / Negative / Positive
700 def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
701 def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
702 def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
703 def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
704 def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
705 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
706
707 // Square root
708 def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
709 def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
710 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
711
712 // Load FP integer
713 def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
714 def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
715 def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
716
717 //===----------------------------------------------------------------------===//
718 // FP: Binary arithmetic
719 //===----------------------------------------------------------------------===//
720
721 // Addition
722 def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
723 def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
724 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
725
726 // Subtraction
727 def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
728 def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
729 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
730
731 // Multiply
732 def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
733 def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
734 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
735 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
736 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
737
738 // Multiply and add / subtract
739 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
740 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
741 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
742 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
743
744 // Division
745 def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
746 def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
747 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
748
749 //===----------------------------------------------------------------------===//
750 // FP: Comparisons
751 //===----------------------------------------------------------------------===//
752
753 // Compare
754 def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
755 def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
756 def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
757
758 // Test Data Class
759 def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
760 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
761
762 }
763