CbC/CbC_llvm: lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp comparison

comparison lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @ 120:1172e4bd9c6f

update 4.0.0

author	mir3636
date	Fri, 25 Nov 2016 19:14:25 +0900
parents	7d135dc70f03
children	803732b1fca8

comparison

equal deleted inserted replaced

-:34baf5011add
+:1172e4bd9c6f
 unsigned GetX86RegNum(const MCOperand &MO) const {
 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
 }
-// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
+unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const {
-// 0-7 and the difference between the 2 groups is given by the REX prefix.
+return Ctx.getRegisterInfo()->getEncodingValue(
-// In the VEX prefix, registers are seen sequencially from 0-15 and encoded
+MI.getOperand(OpNum).getReg());
-// in 1's complement form, example:
+}
-//
-//  ModRM field => XMM9 => 1
+// Does this register require a bit to be set in REX prefix.
-//  VEX.VVVV    => XMM9 => ~9
+bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const {
-//
+return (getX86RegEncoding(MI, OpNum) >> 3) & 1;
-// See table 4-35 of Intel AVX Programming Reference for details.
+}
-unsigned char getVEXRegisterEncoding(const MCInst &MI,
-unsigned OpNum) const {
+void EmitByte(uint8_t C, unsigned &CurByte, raw_ostream &OS) const {
-unsigned SrcReg = MI.getOperand(OpNum).getReg();
-unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
-if (X86II::isX86_64ExtendedReg(SrcReg))
-SrcRegNum |= 8;
-// The registers represented through VEX_VVVV should
-// be encoded in 1's complement form.
-return (~SrcRegNum) & 0xf;
-}
-unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
-unsigned OpNum) const {
-assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
-"Invalid mask register as write-mask!");
-unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
-return MaskRegNum;
-}
-void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
 OS << (char)C;
 ++CurByte;
 }
 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
 unsigned ImmSize, MCFixupKind FixupKind,
 unsigned &CurByte, raw_ostream &OS,
 SmallVectorImpl<MCFixup> &Fixups,
 int ImmOffset = 0) const;
-inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
+inline static uint8_t ModRMByte(unsigned Mod, unsigned RegOpcode,
 unsigned RM) {
 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
 return RM | (RegOpcode << 3) | (Mod << 6);
 }
 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
 unsigned &CurByte, raw_ostream &OS) const {
 // SIB byte is in the same format as the ModRMByte.
 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
 }
+void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
-void EmitMemModRMByte(const MCInst &MI, unsigned Op,
+uint64_t TSFlags, bool Rex, unsigned &CurByte,
-unsigned RegOpcodeField,
+raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
-uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
-SmallVectorImpl<MCFixup> &Fixups,
 const MCSubtargetInfo &STI) const;
 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
 SmallVectorImpl<MCFixup> &Fixups,
 const MCSubtargetInfo &STI) const override;
 raw_ostream &OS) const;
 void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
 const MCInst &MI, raw_ostream &OS) const;
-void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
+bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
 const MCInst &MI, const MCInstrDesc &Desc,
-const MCSubtargetInfo &STI,
+const MCSubtargetInfo &STI, raw_ostream &OS) const;
-raw_ostream &OS) const;
+uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
+int MemOperand, const MCInstrDesc &Desc) const;
 };
 } // end anonymous namespace
 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
 }
 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
 /// sign-extended field.
 static bool isDisp8(int Value) {
-return Value == (signed char)Value;
+return Value == (int8_t)Value;
 }
 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
 /// compressed dispacement field.
 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
 unsigned Mask = CD8_Scale - 1;
 assert((CD8_Scale & Mask) == 0 && "Invalid memory object size.");
 if (Value & Mask) // Unaligned offset
 return false;
 Value /= (int)CD8_Scale;
-bool Ret = (Value == (signed char)Value);
+bool Ret = (Value == (int8_t)Value);
 if (Ret)
 CValue = Value;
 return Ret;
 }
 if ((BaseReg.getReg() != 0 &&
 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
 (IndexReg.getReg() != 0 &&
 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
 return true;
+if (BaseReg.getReg() == X86::EIP) {
+assert(IndexReg.getReg() == 0 && "Invalid eip-based address.");
+return true;
+}
 return false;
 }
 /// Is64BitMemOperand - Return true if the specified instruction has
 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
 // If the fixup is pc-relative, we need to bias the value to be relative to
 // the start of the field, not the end of the field.
 if (FixupKind == FK_PCRel_4 ||
 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
-FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
+FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load) ||
+FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax) ||
+FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex))
 ImmOffset -= 4;
 if (FixupKind == FK_PCRel_2)
 ImmOffset -= 2;
 if (FixupKind == FK_PCRel_1)
 ImmOffset -= 1;
 // Emit a symbolic constant as a fixup and 4 zeros.
 Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc));
 EmitConstant(0, Size, CurByte, OS);
 }
-void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
+void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
 unsigned RegOpcodeField,
-uint64_t TSFlags, unsigned &CurByte,
+uint64_t TSFlags, bool Rex,
-raw_ostream &OS,
+unsigned &CurByte, raw_ostream &OS,
 SmallVectorImpl<MCFixup> &Fixups,
-const MCSubtargetInfo &STI) const{
+const MCSubtargetInfo &STI) const {
 const MCOperand &Disp     = MI.getOperand(Op+X86::AddrDisp);
 const MCOperand &Base     = MI.getOperand(Op+X86::AddrBaseReg);
 const MCOperand &Scale    = MI.getOperand(Op+X86::AddrScaleAmt);
 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
 unsigned BaseReg = Base.getReg();
 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
 // Handle %rip relative addressing.
-if (BaseReg == X86::RIP) {    // [disp32+RIP] in X86-64 mode
+if (BaseReg == X86::RIP ||
+BaseReg == X86::EIP) {    // [disp32+rIP] in X86-64 mode
 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
-unsigned FixupKind = X86::reloc_riprel_4byte;
+unsigned Opcode = MI.getOpcode();
 // movq loads are handled with a special relocation form which allows the
 // linker to eliminate some loads for GOT references which end up in the
 // same linkage unit.
-if (MI.getOpcode() == X86::MOV64rm)
+unsigned FixupKind = [=]() {
-FixupKind = X86::reloc_riprel_4byte_movq_load;
+switch (Opcode) {
+default:
+return X86::reloc_riprel_4byte;
+case X86::MOV64rm:
+assert(Rex);
+return X86::reloc_riprel_4byte_movq_load;
+case X86::CALL64m:
+case X86::JMP64m:
+case X86::TEST64rm:
+case X86::ADC64rm:
+case X86::ADD64rm:
+case X86::AND64rm:
+case X86::CMP64rm:
+case X86::OR64rm:
+case X86::SBB64rm:
+case X86::SUB64rm:
+case X86::XOR64rm:
+return Rex ? X86::reloc_riprel_4byte_relax_rex
+: X86::reloc_riprel_4byte_relax;
+}
+}();
 // rip-relative addressing is actually relative to the *next* instruction.
 // Since an immediate can follow the mod/rm byte for an instruction, this
 // means that we need to bias the immediate field of the instruction with
 // the size of the immediate field.  If we have this case, add it into the
 }
 }
 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
-EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
+unsigned Opcode = MI.getOpcode();
-CurByte, OS, Fixups);
+unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
+: X86::reloc_signed_4byte;
+EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS,
+Fixups);
 return;
 }
 // We need a SIB byte, so start by outputting the ModR/M byte first
 assert(IndexReg.getReg() != X86::ESP &&
 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
 uint64_t Encoding = TSFlags & X86II::EncodingMask;
 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
-bool HasVEX_4VOp3 = TSFlags & X86II::VEX_4VOp3;
-bool HasMemOp4 = TSFlags & X86II::MemOp4;
 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
 // VEX_R: opcode externsion equivalent to REX.R in
 // 1's complement (inverted) form
 //
 //  1: Same as REX_R=0 (must be 1 in 32-bit mode)
 //  0: Same as REX_R=1 (64 bit mode only)
 //
-unsigned char VEX_R = 0x1;
+uint8_t VEX_R = 0x1;
-unsigned char EVEX_R2 = 0x1;
+uint8_t EVEX_R2 = 0x1;
 // VEX_X: equivalent to REX.X, only used when a
 // register is used for index in SIB Byte.
 //
 //  1: Same as REX.X=0 (must be 1 in 32-bit mode)
 //  0: Same as REX.X=1 (64-bit mode only)
-unsigned char VEX_X = 0x1;
+uint8_t VEX_X = 0x1;
 // VEX_B:
 //
 //  1: Same as REX_B=0 (ignored in 32-bit mode)
 //  0: Same as REX_B=1 (64 bit mode only)
 //
-unsigned char VEX_B = 0x1;
+uint8_t VEX_B = 0x1;
 // VEX_W: opcode specific (use like REX.W, or used for
 // opcode extension, or ignored, depending on the opcode byte)
-unsigned char VEX_W = 0;
+uint8_t VEX_W = (TSFlags & X86II::VEX_W) ? 1 : 0;
 // VEX_5M (VEX m-mmmmm field):
 //
 //  0b00000: Reserved for future use
 //  0b00001: implied 0F leading opcode
 //  0b00011: implied 0F 3A leading opcode bytes
 //  0b00100-0b11111: Reserved for future use
 //  0b01000: XOP map select - 08h instructions with imm byte
 //  0b01001: XOP map select - 09h instructions with no imm byte
 //  0b01010: XOP map select - 0Ah instructions with imm dword
-unsigned char VEX_5M = 0;
+uint8_t VEX_5M;
+switch (TSFlags & X86II::OpMapMask) {
+default: llvm_unreachable("Invalid prefix!");
+case X86II::TB:   VEX_5M = 0x1; break; // 0F
+case X86II::T8:   VEX_5M = 0x2; break; // 0F 38
+case X86II::TA:   VEX_5M = 0x3; break; // 0F 3A
+case X86II::XOP8: VEX_5M = 0x8; break;
+case X86II::XOP9: VEX_5M = 0x9; break;
+case X86II::XOPA: VEX_5M = 0xA; break;
+}
 // VEX_4V (VEX vvvv field): a register specifier
 // (in 1's complement form) or 1111 if unused.
-unsigned char VEX_4V = 0xf;
+uint8_t VEX_4V = 0xf;
-unsigned char EVEX_V2 = 0x1;
+uint8_t EVEX_V2 = 0x1;
-// VEX_L (Vector Length):
+// EVEX_L2/VEX_L (Vector Length):
 //
-//  0: scalar or 128-bit vector
+// L2 L
-//  1: 256-bit vector
+//  0 0: scalar or 128-bit vector
+//  0 1: 256-bit vector
+//  1 0: 512-bit vector
 //
-unsigned char VEX_L = 0;
+uint8_t VEX_L = (TSFlags & X86II::VEX_L) ? 1 : 0;
-unsigned char EVEX_L2 = 0;
+uint8_t EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 1 : 0;
 // VEX_PP: opcode extension providing equivalent
 // functionality of a SIMD prefix
 //
 //  0b00: None
 //  0b01: 66
 //  0b10: F3
 //  0b11: F2
 //
-unsigned char VEX_PP = 0;
+uint8_t VEX_PP;
-// EVEX_U
-unsigned char EVEX_U = 1; // Always '1' so far
-// EVEX_z
-unsigned char EVEX_z = 0;
-// EVEX_b
-unsigned char EVEX_b = 0;
-// EVEX_rc
-unsigned char EVEX_rc = 0;
-// EVEX_aaa
-unsigned char EVEX_aaa = 0;
-bool EncodeRC = false;
-if (TSFlags & X86II::VEX_W)
-VEX_W = 1;
-if (TSFlags & X86II::VEX_L)
-VEX_L = 1;
-if (TSFlags & X86II::EVEX_L2)
-EVEX_L2 = 1;
-if (HasEVEX_K && (TSFlags & X86II::EVEX_Z))
-EVEX_z = 1;
-if ((TSFlags & X86II::EVEX_B))
-EVEX_b = 1;
 switch (TSFlags & X86II::OpPrefixMask) {
-default: break; // VEX_PP already correct
+default: llvm_unreachable("Invalid op prefix!");
+case X86II::PS: VEX_PP = 0x0; break; // none
 case X86II::PD: VEX_PP = 0x1; break; // 66
 case X86II::XS: VEX_PP = 0x2; break; // F3
 case X86II::XD: VEX_PP = 0x3; break; // F2
 }
-switch (TSFlags & X86II::OpMapMask) {
+// EVEX_U
-default: llvm_unreachable("Invalid prefix!");
+uint8_t EVEX_U = 1; // Always '1' so far
-case X86II::TB:   VEX_5M = 0x1; break; // 0F
-case X86II::T8:   VEX_5M = 0x2; break; // 0F 38
+// EVEX_z
-case X86II::TA:   VEX_5M = 0x3; break; // 0F 3A
+uint8_t EVEX_z = (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) ? 1 : 0;
-case X86II::XOP8: VEX_5M = 0x8; break;
-case X86II::XOP9: VEX_5M = 0x9; break;
+// EVEX_b
-case X86II::XOPA: VEX_5M = 0xA; break;
+uint8_t EVEX_b = (TSFlags & X86II::EVEX_B) ? 1 : 0;
-}
+// EVEX_rc
+uint8_t EVEX_rc = 0;
+// EVEX_aaa
+uint8_t EVEX_aaa = 0;
+bool EncodeRC = false;
 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
 unsigned NumOps = Desc.getNumOperands();
 unsigned CurOp = X86II::getOperandBias(Desc);
 // MRMDestMem instructions forms:
 //  MemAddr, src1(ModR/M)
 //  MemAddr, src1(VEX_4V), src2(ModR/M)
 //  MemAddr, src1(ModR/M), imm8
 //
-if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
+unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
-X86::AddrBaseReg).getReg()))
+VEX_B = ~(BaseRegEnc >> 3) & 1;
-VEX_B = 0x0;
+unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
-if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
+VEX_X = ~(IndexRegEnc >> 3) & 1;
-X86::AddrIndexReg).getReg()))
+if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
-VEX_X = 0x0;
+EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
-if (X86II::is32ExtendedReg(MI.getOperand(MemOperand +
-X86::AddrIndexReg).getReg()))
-EVEX_V2 = 0x0;
 CurOp += X86::AddrNumOperands;
 if (HasEVEX_K)
-EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
+EVEX_aaa = getX86RegEncoding(MI, CurOp++);
 if (HasVEX_4V) {
-VEX_4V = getVEXRegisterEncoding(MI, CurOp);
+unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_4V = ~VRegEnc & 0xf;
-EVEX_V2 = 0x0;
+EVEX_V2 = ~(VRegEnc >> 4) & 1;
-CurOp++;
+}
-}
+unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
-const MCOperand &MO = MI.getOperand(CurOp);
+VEX_R = ~(RegEnc >> 3) & 1;
-if (MO.isReg()) {
+EVEX_R2 = ~(RegEnc >> 4) & 1;
-if (X86II::isX86_64ExtendedReg(MO.getReg()))
+break;
-VEX_R = 0x0;
+}
-if (X86II::is32ExtendedReg(MO.getReg()))
+case X86II::MRMSrcMem: {
-EVEX_R2 = 0x0;
-}
-break;
-}
-case X86II::MRMSrcMem:
 // MRMSrcMem instructions forms:
 //  src1(ModR/M), MemAddr
 //  src1(ModR/M), src2(VEX_4V), MemAddr
 //  src1(ModR/M), MemAddr, imm8
-//  src1(ModR/M), MemAddr, src2(VEX_I8IMM)
+//  src1(ModR/M), MemAddr, src2(Imm[7:4])
 //
 //  FMA4:
-//  dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
+//  dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
-//  dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
+unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
-if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_R = ~(RegEnc >> 3) & 1;
-VEX_R = 0x0;
+EVEX_R2 = ~(RegEnc >> 4) & 1;
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
-EVEX_R2 = 0x0;
-CurOp++;
 if (HasEVEX_K)
-EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
+EVEX_aaa = getX86RegEncoding(MI, CurOp++);
 if (HasVEX_4V) {
-VEX_4V = getVEXRegisterEncoding(MI, CurOp);
+unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_4V = ~VRegEnc & 0xf;
-EVEX_V2 = 0x0;
+EVEX_V2 = ~(VRegEnc >> 4) & 1;
-CurOp++;
+}
-}
+unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
-if (X86II::isX86_64ExtendedReg(
+VEX_B = ~(BaseRegEnc >> 3) & 1;
-MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
+unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
-VEX_B = 0x0;
+VEX_X = ~(IndexRegEnc >> 3) & 1;
-if (X86II::isX86_64ExtendedReg(
+if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
-MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
+EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
-VEX_X = 0x0;
-if (X86II::is32ExtendedReg(MI.getOperand(MemOperand +
+break;
-X86::AddrIndexReg).getReg()))
+}
-EVEX_V2 = 0x0;
+case X86II::MRMSrcMem4VOp3: {
+// Instruction format for 4VOp3:
-if (HasVEX_4VOp3)
+//   src1(ModR/M), MemAddr, src3(VEX_4V)
-// Instruction format for 4VOp3:
+unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
-//   src1(ModR/M), MemAddr, src3(VEX_4V)
+VEX_R = ~(RegEnc >> 3) & 1;
-// CurOp points to start of the MemoryOperand,
-//   it skips TIED_TO operands if exist, then increments past src1.
+unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
-// CurOp + X86::AddrNumOperands will point to src3.
+VEX_B = ~(BaseRegEnc >> 3) & 1;
-VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
+unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
-break;
+VEX_X = ~(IndexRegEnc >> 3) & 1;
+VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf;
+break;
+}
+case X86II::MRMSrcMemOp4: {
+//  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
+unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
+VEX_R = ~(RegEnc >> 3) & 1;
+unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
+VEX_4V = ~VRegEnc & 0xf;
+unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
+VEX_B = ~(BaseRegEnc >> 3) & 1;
+unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
+VEX_X = ~(IndexRegEnc >> 3) & 1;
+break;
+}
 case X86II::MRM0m: case X86II::MRM1m:
 case X86II::MRM2m: case X86II::MRM3m:
 case X86II::MRM4m: case X86II::MRM5m:
 case X86II::MRM6m: case X86II::MRM7m: {
 // MRM[0-9]m instructions forms:
 //  MemAddr
 //  src1(VEX_4V), MemAddr
 if (HasVEX_4V) {
-VEX_4V = getVEXRegisterEncoding(MI, CurOp);
+unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_4V = ~VRegEnc & 0xf;
-EVEX_V2 = 0x0;
+EVEX_V2 = ~(VRegEnc >> 4) & 1;
-CurOp++;
 }
 if (HasEVEX_K)
-EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
+EVEX_aaa = getX86RegEncoding(MI, CurOp++);
-if (X86II::isX86_64ExtendedReg(
+unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
-MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
+VEX_B = ~(BaseRegEnc >> 3) & 1;
-VEX_B = 0x0;
+unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
-if (X86II::isX86_64ExtendedReg(
+VEX_X = ~(IndexRegEnc >> 3) & 1;
-MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
+break;
-VEX_X = 0x0;
+}
-break;
+case X86II::MRMSrcReg: {
-}
-case X86II::MRMSrcReg:
 // MRMSrcReg instructions forms:
-//  dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
+//  dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
 //  dst(ModR/M), src1(ModR/M)
 //  dst(ModR/M), src1(ModR/M), imm8
 //
 //  FMA4:
-//  dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
+//  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
-//  dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
+unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
-if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_R = ~(RegEnc >> 3) & 1;
-VEX_R = 0x0;
+EVEX_R2 = ~(RegEnc >> 4) & 1;
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
-EVEX_R2 = 0x0;
-CurOp++;
 if (HasEVEX_K)
-EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
+EVEX_aaa = getX86RegEncoding(MI, CurOp++);
 if (HasVEX_4V) {
-VEX_4V = getVEXRegisterEncoding(MI, CurOp);
+unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_4V = ~VRegEnc & 0xf;
-EVEX_V2 = 0x0;
+EVEX_V2 = ~(VRegEnc >> 4) & 1;
-CurOp++;
+}
-}
+RegEnc = getX86RegEncoding(MI, CurOp++);
-if (HasMemOp4) // Skip second register source (encoded in I8IMM)
+VEX_B = ~(RegEnc >> 3) & 1;
-CurOp++;
+VEX_X = ~(RegEnc >> 4) & 1;
-if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
-VEX_B = 0x0;
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
-VEX_X = 0x0;
-CurOp++;
-if (HasVEX_4VOp3)
-VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
 if (EVEX_b) {
 if (HasEVEX_RC) {
 unsigned RcOperand = NumOps-1;
 assert(RcOperand >= CurOp);
 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
 }
 EncodeRC = true;
 }
 break;
-case X86II::MRMDestReg:
+}
+case X86II::MRMSrcReg4VOp3: {
+// Instruction format for 4VOp3:
+//   src1(ModR/M), src2(ModR/M), src3(VEX_4V)
+unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
+VEX_R = ~(RegEnc >> 3) & 1;
+RegEnc = getX86RegEncoding(MI, CurOp++);
+VEX_B = ~(RegEnc >> 3) & 1;
+VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf;
+break;
+}
+case X86II::MRMSrcRegOp4: {
+//  dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
+unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
+VEX_R = ~(RegEnc >> 3) & 1;
+unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
+VEX_4V = ~VRegEnc & 0xf;
+// Skip second register source (encoded in Imm[7:4])
+++CurOp;
+RegEnc = getX86RegEncoding(MI, CurOp++);
+VEX_B = ~(RegEnc >> 3) & 1;
+VEX_X = ~(RegEnc >> 4) & 1;
+break;
+}
+case X86II::MRMDestReg: {
 // MRMDestReg instructions forms:
 //  dst(ModR/M), src(ModR/M)
 //  dst(ModR/M), src(ModR/M), imm8
 //  dst(ModR/M), src1(VEX_4V), src2(ModR/M)
-if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
+unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
-VEX_B = 0x0;
+VEX_B = ~(RegEnc >> 3) & 1;
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_X = ~(RegEnc >> 4) & 1;
-VEX_X = 0x0;
-CurOp++;
 if (HasEVEX_K)
-EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
+EVEX_aaa = getX86RegEncoding(MI, CurOp++);
 if (HasVEX_4V) {
-VEX_4V = getVEXRegisterEncoding(MI, CurOp);
+unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_4V = ~VRegEnc & 0xf;
-EVEX_V2 = 0x0;
+EVEX_V2 = ~(VRegEnc >> 4) & 1;
-CurOp++;
+}
-}
+RegEnc = getX86RegEncoding(MI, CurOp++);
-if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_R = ~(RegEnc >> 3) & 1;
-VEX_R = 0x0;
+EVEX_R2 = ~(RegEnc >> 4) & 1;
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
-EVEX_R2 = 0x0;
 if (EVEX_b)
 EncodeRC = true;
 break;
+}
 case X86II::MRM0r: case X86II::MRM1r:
 case X86II::MRM2r: case X86II::MRM3r:
 case X86II::MRM4r: case X86II::MRM5r:
-case X86II::MRM6r: case X86II::MRM7r:
+case X86II::MRM6r: case X86II::MRM7r: {
 // MRM0r-MRM7r instructions forms:
 //  dst(VEX_4V), src(ModR/M), imm8
 if (HasVEX_4V) {
-VEX_4V = getVEXRegisterEncoding(MI, CurOp);
+unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_4V = ~VRegEnc & 0xf;
-EVEX_V2 = 0x0;
+EVEX_V2 = ~(VRegEnc >> 4) & 1;
-CurOp++;
 }
 if (HasEVEX_K)
-EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
+EVEX_aaa = getX86RegEncoding(MI, CurOp++);
-if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
+unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
-VEX_B = 0x0;
+VEX_B = ~(RegEnc >> 3) & 1;
-if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
+VEX_X = ~(RegEnc >> 4) & 1;
-VEX_X = 0x0;
+break;
-break;
+}
 }
 if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
 // VEX opcode prefix can have 2 or 3 bytes
 //
 //
 //  XOP uses a similar prefix:
 //    +-----+ +--------------+ +-------------------+
 //    | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
 //    +-----+ +--------------+ +-------------------+
-unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
+uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
 // Can we use the 2 byte VEX prefix?
 if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
 EmitByte(0xC5, CurByte, OS);
 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
 // +-----+ +--------------+ +-------------------+ +------------------------+
 assert((VEX_5M & 0x3) == VEX_5M
 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
-VEX_5M &= 0x3;
 EmitByte(0x62, CurByte, OS);
 EmitByte((VEX_R   << 7) |
 (VEX_X   << 6) |
 (VEX_B   << 5) |
 (EVEX_R2 << 4) |
 (VEX_4V  << 3) |
 (EVEX_U  << 2) |
 VEX_PP, CurByte, OS);
 if (EncodeRC)
 EmitByte((EVEX_z  << 7) |
 (EVEX_rc << 5) |
 (EVEX_b  << 4) |
 (EVEX_V2 << 3) |
 EVEX_aaa, CurByte, OS);
 else
 EmitByte((EVEX_z  << 7) |
 (EVEX_L2 << 6) |
 (VEX_L   << 5) |
 (EVEX_b  << 4) |
 (EVEX_V2 << 3) |
 EVEX_aaa, CurByte, OS);
 }
 }
 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
 /// size, and 3) use of X86-64 extended registers.
-static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
+uint8_t X86MCCodeEmitter::DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
-const MCInstrDesc &Desc) {
+int MemOperand,
-unsigned REX = 0;
+const MCInstrDesc &Desc) const {
+uint8_t REX = 0;
 bool UsesHighByteReg = false;
 if (TSFlags & X86II::REX_W)
 REX |= 1 << 3; // set REX.W
 if (MI.getNumOperands() == 0) return REX;
 unsigned NumOps = MI.getNumOperands();
-// FIXME: MCInst should explicitize the two-addrness.
+unsigned CurOp = X86II::getOperandBias(Desc);
-bool isTwoAddr = NumOps > 1 &&
-Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
-unsigned i = isTwoAddr ? 1 : 0;
+for (unsigned i = CurOp; i != NumOps; ++i) {
-for (; i != NumOps; ++i) {
 const MCOperand &MO = MI.getOperand(i);
 if (!MO.isReg()) continue;
 unsigned Reg = MO.getReg();
 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
 UsesHighByteReg = true;
-if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
+if (X86II::isX86_64NonExtLowByteReg(Reg))
 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
 // that returns non-zero.
 REX |= 0x40; // REX fixed encoding prefix
-break;
 }
 switch (TSFlags & X86II::FormMask) {
+case X86II::AddRegFrm:
+REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
+break;
 case X86II::MRMSrcReg:
-if (MI.getOperand(0).isReg() &&
+REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
-X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
+REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
-REX |= 1 << 2; // set REX.R
-i = isTwoAddr ? 2 : 1;
-for (; i != NumOps; ++i) {
-const MCOperand &MO = MI.getOperand(i);
-if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
-REX |= 1 << 0; // set REX.B
-}
 break;
 case X86II::MRMSrcMem: {
-if (MI.getOperand(0).isReg() &&
+REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
-X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
+REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
-REX |= 1 << 2; // set REX.R
+REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
-unsigned Bit = 0;
+CurOp += X86::AddrNumOperands;
-i = isTwoAddr ? 2 : 1;
+break;
-for (; i != NumOps; ++i) {
+}
-const MCOperand &MO = MI.getOperand(i);
+case X86II::MRMDestReg:
-if (MO.isReg()) {
+REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
-if (X86II::isX86_64ExtendedReg(MO.getReg()))
+REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
-REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
+break;
-Bit++;
+case X86II::MRMDestMem:
-}
+REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
-}
+REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
-break;
+CurOp += X86::AddrNumOperands;
-}
+REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
+break;
 case X86II::MRMXm:
 case X86II::MRM0m: case X86II::MRM1m:
 case X86II::MRM2m: case X86II::MRM3m:
 case X86II::MRM4m: case X86II::MRM5m:
 case X86II::MRM6m: case X86II::MRM7m:
-case X86II::MRMDestMem: {
+REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
-unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
+REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
-i = isTwoAddr ? 1 : 0;
+break;
-if (NumOps > e && MI.getOperand(e).isReg() &&
+case X86II::MRMXr:
-X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
+case X86II::MRM0r: case X86II::MRM1r:
-REX |= 1 << 2; // set REX.R
+case X86II::MRM2r: case X86II::MRM3r:
-unsigned Bit = 0;
+case X86II::MRM4r: case X86II::MRM5r:
-for (; i != e; ++i) {
+case X86II::MRM6r: case X86II::MRM7r:
-const MCOperand &MO = MI.getOperand(i);
+REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
-if (MO.isReg()) {
-if (X86II::isX86_64ExtendedReg(MO.getReg()))
-REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
-Bit++;
-}
-}
-break;
-}
-default:
-if (MI.getOperand(0).isReg() &&
-X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
-REX |= 1 << 0; // set REX.B
-i = isTwoAddr ? 2 : 1;
-for (unsigned e = NumOps; i != e; ++i) {
-const MCOperand &MO = MI.getOperand(i);
-if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
-REX |= 1 << 2; // set REX.R
-}
 break;
 }
 if (REX && UsesHighByteReg)
 report_fatal_error("Cannot encode high byte register in REX-prefixed instruction");
 case X86::FS: EmitByte(0x64, CurByte, OS); break;
 case X86::GS: EmitByte(0x65, CurByte, OS); break;
 }
 }
-/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
+/// Emit all instruction prefixes prior to the opcode.
 ///
 /// MemOperand is the operand # of the start of a memory operand if present.  If
 /// Not present, it is -1.
-void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
+///
+/// Returns true if a REX prefix was used.
+bool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
 int MemOperand, const MCInst &MI,
 const MCInstrDesc &Desc,
 const MCSubtargetInfo &STI,
 raw_ostream &OS) const {
+bool Ret = false;
 // Emit the operand size opcode prefix as needed.
 if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32
 : X86II::OpSize16))
 EmitByte(0x66, CurByte, OS);
 }
 // Handle REX prefix.
 // FIXME: Can this come before F2 etc to simplify emission?
 if (is64BitMode(STI)) {
-if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
+if (uint8_t REX = DetermineREXPrefix(MI, TSFlags, MemOperand, Desc)) {
 EmitByte(0x40 | REX, CurByte, OS);
+Ret = true;
+}
 }
 // 0x0F escape code must be emitted just before the opcode.
 switch (TSFlags & X86II::OpMapMask) {
 case X86II::TB:  // Two-byte opcode map
 break;
 case X86II::TA:    // 0F 3A
 EmitByte(0x3A, CurByte, OS);
 break;
 }
+return Ret;
 }
 void X86MCCodeEmitter::
 encodeInstruction(const MCInst &MI, raw_ostream &OS,
 SmallVectorImpl<MCFixup> &Fixups,
 // Encoding type for this instruction.
 uint64_t Encoding = TSFlags & X86II::EncodingMask;
 // It uses the VEX.VVVV field?
 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
-bool HasVEX_4VOp3 = TSFlags & X86II::VEX_4VOp3;
+bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
-bool HasMemOp4 = TSFlags & X86II::MemOp4;
-const unsigned MemOp4_I8IMMOperand = 2;
 // It uses the EVEX.aaa field?
 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
+// Used if a register is encoded in 7:4 of immediate.
+unsigned I8RegNum = 0;
 // Determine where the memory operand starts, if present.
-int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
+int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
 if (MemoryOperand != -1) MemoryOperand += CurOp;
 // Emit segment override opcode prefix as needed.
 if (MemoryOperand >= 0)
 EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg,
 }
 if (need_address_override)
 EmitByte(0x67, CurByte, OS);
+bool Rex = false;
 if (Encoding == 0)
-EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
+Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
 else
 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
-unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
+uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
 if (TSFlags & X86II::Has3DNow0F0FOpcode)
 BaseOpcode = 0x0F;   // Weird 3DNow! encoding.
-unsigned SrcRegNum = 0;
+uint64_t Form = TSFlags & X86II::FormMask;
-switch (TSFlags & X86II::FormMask) {
+switch (Form) {
-default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
+default: errs() << "FORM: " << Form << "\n";
 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
 case X86II::Pseudo:
 llvm_unreachable("Pseudo instruction shouldn't be emitted");
 case X86II::RawFrmDstSrc: {
 unsigned siReg = MI.getOperand(1).getReg();
 case X86II::AddRegFrm:
 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
 break;
-case X86II::MRMDestReg:
+case X86II::MRMDestReg: {
 EmitByte(BaseOpcode, CurByte, OS);
-SrcRegNum = CurOp + 1;
+unsigned SrcRegNum = CurOp + 1;
 if (HasEVEX_K) // Skip writemask
-SrcRegNum++;
+++SrcRegNum;
 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
 ++SrcRegNum;
 EmitRegModRMByte(MI.getOperand(CurOp),
 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
 CurOp = SrcRegNum + 1;
 break;
+}
-case X86II::MRMDestMem:
+case X86II::MRMDestMem: {
 EmitByte(BaseOpcode, CurByte, OS);
-SrcRegNum = CurOp + X86::AddrNumOperands;
+unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
 if (HasEVEX_K) // Skip writemask
-SrcRegNum++;
+++SrcRegNum;
 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
 ++SrcRegNum;
-EmitMemModRMByte(MI, CurOp,
+emitMemModRMByte(MI, CurOp, GetX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
-GetX86RegNum(MI.getOperand(SrcRegNum)),
+Rex, CurByte, OS, Fixups, STI);
-TSFlags, CurByte, OS, Fixups, STI);
 CurOp = SrcRegNum + 1;
 break;
+}
-case X86II::MRMSrcReg:
+case X86II::MRMSrcReg: {
 EmitByte(BaseOpcode, CurByte, OS);
-SrcRegNum = CurOp + 1;
+unsigned SrcRegNum = CurOp + 1;
 if (HasEVEX_K) // Skip writemask
-SrcRegNum++;
+++SrcRegNum;
 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
 ++SrcRegNum;
-if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
-++SrcRegNum;
 EmitRegModRMByte(MI.getOperand(SrcRegNum),
 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
+CurOp = SrcRegNum + 1;
-// 2 operands skipped with HasMemOp4, compensate accordingly
+if (HasVEX_I8Reg)
-CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
+I8RegNum = getX86RegEncoding(MI, CurOp++);
-if (HasVEX_4VOp3)
-++CurOp;
 // do not count the rounding control operand
 if (HasEVEX_RC)
-NumOps--;
+--NumOps;
 break;
+}
+case X86II::MRMSrcReg4VOp3: {
+EmitByte(BaseOpcode, CurByte, OS);
+unsigned SrcRegNum = CurOp + 1;
+EmitRegModRMByte(MI.getOperand(SrcRegNum),
+GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
+CurOp = SrcRegNum + 1;
+++CurOp; // Encoded in VEX.VVVV
+break;
+}
+case X86II::MRMSrcRegOp4: {
+EmitByte(BaseOpcode, CurByte, OS);
+unsigned SrcRegNum = CurOp + 1;
+// Skip 1st src (which is encoded in VEX_VVVV)
+++SrcRegNum;
+// Capture 2nd src (which is encoded in Imm[7:4])
+assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
+I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
+EmitRegModRMByte(MI.getOperand(SrcRegNum),
+GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
+CurOp = SrcRegNum + 1;
+break;
+}
 case X86II::MRMSrcMem: {
-int AddrOperands = X86::AddrNumOperands;
 unsigned FirstMemOp = CurOp+1;
-if (HasEVEX_K) { // Skip writemask
+if (HasEVEX_K) // Skip writemask
-++AddrOperands;
 ++FirstMemOp;
-}
+if (HasVEX_4V)
-if (HasVEX_4V) {
-++AddrOperands;
 ++FirstMemOp;  // Skip the register source (which is encoded in VEX_VVVV).
-}
-if (HasMemOp4) // Skip second register source (encoded in I8IMM)
+EmitByte(BaseOpcode, CurByte, OS);
-++FirstMemOp;
+emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
-EmitByte(BaseOpcode, CurByte, OS);
+TSFlags, Rex, CurByte, OS, Fixups, STI);
+CurOp = FirstMemOp + X86::AddrNumOperands;
-EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
+if (HasVEX_I8Reg)
-TSFlags, CurByte, OS, Fixups, STI);
+I8RegNum = getX86RegEncoding(MI, CurOp++);
-CurOp += AddrOperands + 1;
+break;
-if (HasVEX_4VOp3)
+}
-++CurOp;
+case X86II::MRMSrcMem4VOp3: {
+unsigned FirstMemOp = CurOp+1;
+EmitByte(BaseOpcode, CurByte, OS);
+emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
+TSFlags, Rex, CurByte, OS, Fixups, STI);
+CurOp = FirstMemOp + X86::AddrNumOperands;
+++CurOp; // Encoded in VEX.VVVV.
+break;
+}
+case X86II::MRMSrcMemOp4: {
+unsigned FirstMemOp = CurOp+1;
+++FirstMemOp;  // Skip the register source (which is encoded in VEX_VVVV).
+// Capture second register source (encoded in Imm[7:4])
+assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
+I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
+EmitByte(BaseOpcode, CurByte, OS);
+emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
+TSFlags, Rex, CurByte, OS, Fixups, STI);
+CurOp = FirstMemOp + X86::AddrNumOperands;
 break;
 }
 case X86II::MRMXr:
 case X86II::MRM0r: case X86II::MRM1r:
 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
 ++CurOp;
 if (HasEVEX_K) // Skip writemask
 ++CurOp;
 EmitByte(BaseOpcode, CurByte, OS);
-uint64_t Form = TSFlags & X86II::FormMask;
 EmitRegModRMByte(MI.getOperand(CurOp++),
 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
 CurByte, OS);
 break;
 }
 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
 ++CurOp;
 if (HasEVEX_K) // Skip writemask
 ++CurOp;
 EmitByte(BaseOpcode, CurByte, OS);
-uint64_t Form = TSFlags & X86II::FormMask;
+emitMemModRMByte(MI, CurOp,
-EmitMemModRMByte(MI, CurOp, (Form == X86II::MRMXm) ? 0 : Form-X86II::MRM0m,
+(Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
-TSFlags, CurByte, OS, Fixups, STI);
+Rex, CurByte, OS, Fixups, STI);
 CurOp += X86::AddrNumOperands;
 break;
 }
 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
 case X86II::MRM_FF:
 EmitByte(BaseOpcode, CurByte, OS);
-uint64_t Form = TSFlags & X86II::FormMask;
 EmitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS);
 break;
 }
-// If there is a remaining operand, it must be a trailing immediate.  Emit it
+if (HasVEX_I8Reg) {
-// according to the right size for the instruction. Some instructions
-// (SSE4a extrq and insertq) have two trailing immediates.
-while (CurOp != NumOps && NumOps - CurOp <= 2) {
 // The last source register of a 4 operand instruction in AVX is encoded
 // in bits[7:4] of a immediate byte.
-if (TSFlags & X86II::VEX_I8IMM) {
+assert(I8RegNum < 16 && "Register encoding out of range");
-const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
+I8RegNum <<= 4;
-: CurOp);
+if (CurOp != NumOps) {
-++CurOp;
+unsigned Val = MI.getOperand(CurOp++).getImm();
-unsigned RegNum = GetX86RegNum(MO) << 4;
+assert(Val < 16 && "Immediate operand value out of range");
-if (X86II::isX86_64ExtendedReg(MO.getReg()))
+I8RegNum |= Val;
-RegNum |= 1 << 7;
+}
-// If there is an additional 5th operand it must be an immediate, which
+EmitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
-// is encoded in bits[3:0]
+CurByte, OS, Fixups);
-if (CurOp != NumOps) {
+} else {
-const MCOperand &MIMM = MI.getOperand(CurOp++);
+// If there is a remaining operand, it must be a trailing immediate. Emit it
-if (MIMM.isImm()) {
+// according to the right size for the instruction. Some instructions
-unsigned Val = MIMM.getImm();
+// (SSE4a extrq and insertq) have two trailing immediates.
-assert(Val < 16 && "Immediate operand value out of range");
+while (CurOp != NumOps && NumOps - CurOp <= 2) {
-RegNum |= Val;
-}
-}
-EmitImmediate(MCOperand::createImm(RegNum), MI.getLoc(), 1, FK_Data_1,
-CurByte, OS, Fixups);
-} else {
 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
 CurByte, OS, Fixups);
 }
 }

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @ 120:1172e4bd9c6f