comparison test/CodeGen/AArch64/arm64-fast-isel-gv.ll @ 120:1172e4bd9c6f

update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 3a76565eade5
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
16 define i32 @Rand() nounwind { 16 define i32 @Rand() nounwind {
17 entry: 17 entry:
18 ; CHECK: @Rand 18 ; CHECK: @Rand
19 ; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE 19 ; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
20 ; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}} 20 ; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}}
21 ; CHECK: movz [[REG3:x[0-9]+]], #0x3619 21 ; CHECK: mov [[REG3:x[0-9]+]], #13849
22 ; CHECK: movz [[REG4:x[0-9]+]], #0x51d 22 ; CHECK: mov [[REG4:x[0-9]+]], #1309
23 ; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}} 23 ; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}}
24 ; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]] 24 ; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]]
25 ; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]] 25 ; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]]
26 ; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff 26 ; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff
27 ; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}} 27 ; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}}