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comparison test/Transforms/LoopVectorize/if-pred-stores.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
1 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -simplifycfg < %s | FileCheck %s --check-prefix=UNROLL 1 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=UNROLL
2 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize < %s | FileCheck %s --check-prefix=UNROLL-NOSIMPLIFY 2 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info < %s | FileCheck %s --check-prefix=UNROLL-NOSIMPLIFY
3 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -enable-cond-stores-vec -simplifycfg < %s | FileCheck %s --check-prefix=VEC 3 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -enable-cond-stores-vec -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=VEC
4 ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -enable-cond-stores-vec -simplifycfg -instcombine < %s | FileCheck %s --check-prefix=VEC-IC
5 4
6 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" 5 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
7 target triple = "x86_64-apple-macosx10.9.0"
8 6
9 ; Test predication of stores. 7 ; Test predication of stores.
10 define i32 @test(i32* nocapture %f) #0 { 8 define i32 @test(i32* nocapture %f) #0 {
11 entry: 9 entry:
12 br label %for.body 10 br label %for.body
13 11
14 ; VEC-LABEL: test 12 ; VEC-LABEL: test
13 ; VEC: %[[v0:.+]] = add i64 %index, 0
15 ; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100> 14 ; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
16 ; VEC: %[[v9:.+]] = add nsw <2 x i32> %{{.*}}, <i32 20, i32 20> 15 ; VEC: %[[v9:.+]] = add nsw <2 x i32> %{{.*}}, <i32 20, i32 20>
17 ; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true> 16 ; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true>
18 ; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[v10]], i32 0 17 ; VEC: %[[o1:.+]] = or <2 x i1> zeroinitializer, %[[v10]]
18 ; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[o1]], i32 0
19 ; VEC: %[[v12:.+]] = icmp eq i1 %[[v11]], true 19 ; VEC: %[[v12:.+]] = icmp eq i1 %[[v11]], true
20 ; VEC: %[[v13:.+]] = extractelement <2 x i32> %[[v9]], i32 0
21 ; VEC: %[[v14:.+]] = extractelement <2 x i32*> %{{.*}}, i32 0
22 ; VEC: br i1 %[[v12]], label %[[cond:.+]], label %[[else:.+]] 20 ; VEC: br i1 %[[v12]], label %[[cond:.+]], label %[[else:.+]]
23 ; 21 ;
24 ; VEC: [[cond]]: 22 ; VEC: [[cond]]:
25 ; VEC: store i32 %[[v13]], i32* %[[v14]], align 4 23 ; VEC: %[[v13:.+]] = extractelement <2 x i32> %[[v9]], i32 0
24 ; VEC: %[[v2:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v0]]
25 ; VEC: store i32 %[[v13]], i32* %[[v2]], align 4
26 ; VEC: br label %[[else:.+]] 26 ; VEC: br label %[[else:.+]]
27 ; 27 ;
28 ; VEC: [[else]]: 28 ; VEC: [[else]]:
29 ; VEC: %[[v15:.+]] = extractelement <2 x i1> %[[v10]], i32 1 29 ; VEC: %[[v15:.+]] = extractelement <2 x i1> %[[o1]], i32 1
30 ; VEC: %[[v16:.+]] = icmp eq i1 %[[v15]], true 30 ; VEC: %[[v16:.+]] = icmp eq i1 %[[v15]], true
31 ; VEC: %[[v17:.+]] = extractelement <2 x i32> %[[v9]], i32 1
32 ; VEC: %[[v18:.+]] = extractelement <2 x i32*> %{{.+}} i32 1
33 ; VEC: br i1 %[[v16]], label %[[cond2:.+]], label %[[else2:.+]] 31 ; VEC: br i1 %[[v16]], label %[[cond2:.+]], label %[[else2:.+]]
34 ; 32 ;
35 ; VEC: [[cond2]]: 33 ; VEC: [[cond2]]:
36 ; VEC: store i32 %[[v17]], i32* %[[v18]], align 4 34 ; VEC: %[[v17:.+]] = extractelement <2 x i32> %[[v9]], i32 1
35 ; VEC: %[[v1:.+]] = add i64 %index, 1
36 ; VEC: %[[v4:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v1]]
37 ; VEC: store i32 %[[v17]], i32* %[[v4]], align 4
37 ; VEC: br label %[[else2:.+]] 38 ; VEC: br label %[[else2:.+]]
38 ; 39 ;
39 ; VEC: [[else2]]: 40 ; VEC: [[else2]]:
40
41 ; VEC-IC-LABEL: test
42 ; VEC-IC: %[[v1:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
43 ; VEC-IC: %[[v2:.+]] = add nsw <2 x i32> %{{.*}}, <i32 20, i32 20>
44 ; VEC-IC: %[[v3:.+]] = extractelement <2 x i1> %[[v1]], i32 0
45 ; VEC-IC: br i1 %[[v3]], label %[[cond:.+]], label %[[else:.+]]
46 ;
47 ; VEC-IC: [[cond]]:
48 ; VEC-IC: %[[v4:.+]] = extractelement <2 x i32> %[[v2]], i32 0
49 ; VEC-IC: store i32 %[[v4]], i32* %{{.*}}, align 4
50 ; VEC-IC: br label %[[else:.+]]
51 ;
52 ; VEC-IC: [[else]]:
53 ; VEC-IC: %[[v5:.+]] = extractelement <2 x i1> %[[v1]], i32 1
54 ; VEC-IC: br i1 %[[v5]], label %[[cond2:.+]], label %[[else2:.+]]
55 ;
56 ; VEC-IC: [[cond2]]:
57 ; VEC-IC: %[[v6:.+]] = extractelement <2 x i32> %[[v2]], i32 1
58 ; VEC-IC: store i32 %[[v6]], i32* %{{.*}}, align 4
59 ; VEC-IC: br label %[[else2:.+]]
60 ;
61 ; VEC-IC: [[else2]]:
62 41
63 ; UNROLL-LABEL: test 42 ; UNROLL-LABEL: test
64 ; UNROLL: vector.body: 43 ; UNROLL: vector.body:
65 ; UNROLL: %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 0 44 ; UNROLL: %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 0
66 ; UNROLL: %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 1 45 ; UNROLL: %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 1
68 ; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]] 47 ; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]]
69 ; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4 48 ; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4
70 ; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4 49 ; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4
71 ; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100 50 ; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100
72 ; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100 51 ; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100
73 ; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20 52 ; UNROLL: %[[o1:[a-zA-Z0-9]+]] = or i1 false, %[[v4]]
74 ; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20 53 ; UNROLL: %[[o2:[a-zA-Z0-9]+]] = or i1 false, %[[v5]]
75 ; UNROLL: %[[v8:[a-zA-Z0-9]+]] = icmp eq i1 %[[v4]], true 54 ; UNROLL: %[[v8:[a-zA-Z0-9]+]] = icmp eq i1 %[[o1]], true
76 ; UNROLL: br i1 %[[v8]], label %[[cond:[a-zA-Z0-9.]+]], label %[[else:[a-zA-Z0-9.]+]] 55 ; UNROLL: br i1 %[[v8]], label %[[cond:[a-zA-Z0-9.]+]], label %[[else:[a-zA-Z0-9.]+]]
77 ; 56 ;
78 ; UNROLL: [[cond]]: 57 ; UNROLL: [[cond]]:
58 ; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20
79 ; UNROLL: store i32 %[[v6]], i32* %[[v0]], align 4 59 ; UNROLL: store i32 %[[v6]], i32* %[[v0]], align 4
80 ; UNROLL: br label %[[else]] 60 ; UNROLL: br label %[[else]]
81 ; 61 ;
82 ; UNROLL: [[else]]: 62 ; UNROLL: [[else]]:
83 ; UNROLL: %[[v9:[a-zA-Z0-9]+]] = icmp eq i1 %[[v5]], true 63 ; UNROLL: %[[v9:[a-zA-Z0-9]+]] = icmp eq i1 %[[o2]], true
84 ; UNROLL: br i1 %[[v9]], label %[[cond2:[a-zA-Z0-9.]+]], label %[[else2:[a-zA-Z0-9.]+]] 64 ; UNROLL: br i1 %[[v9]], label %[[cond2:[a-zA-Z0-9.]+]], label %[[else2:[a-zA-Z0-9.]+]]
85 ; 65 ;
86 ; UNROLL: [[cond2]]: 66 ; UNROLL: [[cond2]]:
67 ; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20
87 ; UNROLL: store i32 %[[v7]], i32* %[[v1]], align 4 68 ; UNROLL: store i32 %[[v7]], i32* %[[v1]], align 4
88 ; UNROLL: br label %[[else2]] 69 ; UNROLL: br label %[[else2]]
89 ; 70 ;
90 ; UNROLL: [[else2]]: 71 ; UNROLL: [[else2]]:
91 72