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comparison llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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children 5f17cb93ff66
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147:c2174574ed3a 150:1d019706d866
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s
3
4 # FIXME: This is a miscompile, and the s_or_b64s need to be preserved.
5
6 ---
7 name: invalid_end_cf_fold_0
8 tracksRegLiveness: true
9 liveins:
10 - { reg: '$vgpr0', virtual-reg: '%0' }
11 - { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
12 machineFunctionInfo:
13 isEntryFunction: true
14 body: |
15 ; GXN-LABEL: name: invalid_end_cf_fold_0
16 ; GXN: bb.0:
17 ; GXN: successors: %bb.1(0x80000000)
18 ; GXN: liveins: $vgpr0, $sgpr0_sgpr1
19 ; GXN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
20 ; GXN: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
21 ; GXN: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $exec
22 ; GXN: bb.1:
23 ; GXN: successors: %bb.2(0x80000000)
24 ; GXN: bb.2:
25 ; GXN: $exec = S_OR_B64 $exec, [[COPY1]], implicit-def $scc
26 ; GXN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
27 ; GXN: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
28 ; GXN: DS_WRITE_B32 [[DEF]], [[DEF1]], 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3)
29 ; GXN: S_ENDPGM 0
30 bb.0:
31 liveins: $vgpr0, $sgpr0_sgpr1
32
33 %0:sgpr_64 = COPY $sgpr0_sgpr1
34 %1:sgpr_64 = COPY $exec
35 $exec = S_OR_B64 $exec, %0, implicit-def $scc
36 %2:sgpr_64 = COPY $exec
37
38 bb.1:
39 $exec = S_OR_B64 $exec, %1, implicit-def $scc
40
41 bb.2:
42 $exec = S_OR_B64 $exec, %2, implicit-def $scc
43
44 %5:vgpr_32 = IMPLICIT_DEF
45 %6:vgpr_32 = IMPLICIT_DEF
46 DS_WRITE_B32 %5, %6, 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3)
47 S_ENDPGM 0
48
49 ...