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comparison llvm/test/CodeGen/AMDGPU/rotr.ll @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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children 2e18cbf3894f
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147:c2174574ed3a 150:1d019706d866
1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
4
5 ; FUNC-LABEL: {{^}}rotr_i32:
6 ; R600: BIT_ALIGN_INT
7
8 ; SI: v_alignbit_b32
9 define amdgpu_kernel void @rotr_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) {
10 entry:
11 %tmp0 = sub i32 32, %y
12 %tmp1 = shl i32 %x, %tmp0
13 %tmp2 = lshr i32 %x, %y
14 %tmp3 = or i32 %tmp1, %tmp2
15 store i32 %tmp3, i32 addrspace(1)* %in
16 ret void
17 }
18
19 ; FUNC-LABEL: {{^}}rotr_v2i32:
20 ; R600: BIT_ALIGN_INT
21 ; R600: BIT_ALIGN_INT
22
23 ; SI: v_alignbit_b32
24 ; SI: v_alignbit_b32
25 define amdgpu_kernel void @rotr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
26 entry:
27 %tmp0 = sub <2 x i32> <i32 32, i32 32>, %y
28 %tmp1 = shl <2 x i32> %x, %tmp0
29 %tmp2 = lshr <2 x i32> %x, %y
30 %tmp3 = or <2 x i32> %tmp1, %tmp2
31 store <2 x i32> %tmp3, <2 x i32> addrspace(1)* %in
32 ret void
33 }
34
35 ; FUNC-LABEL: {{^}}rotr_v4i32:
36 ; R600: BIT_ALIGN_INT
37 ; R600: BIT_ALIGN_INT
38 ; R600: BIT_ALIGN_INT
39 ; R600: BIT_ALIGN_INT
40
41 ; SI: v_alignbit_b32
42 ; SI: v_alignbit_b32
43 ; SI: v_alignbit_b32
44 ; SI: v_alignbit_b32
45 define amdgpu_kernel void @rotr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
46 entry:
47 %tmp0 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
48 %tmp1 = shl <4 x i32> %x, %tmp0
49 %tmp2 = lshr <4 x i32> %x, %y
50 %tmp3 = or <4 x i32> %tmp1, %tmp2
51 store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %in
52 ret void
53 }