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annotate llvm/test/CodeGen/AMDGPU/rotr.ll @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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children 2e18cbf3894f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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150
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1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
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2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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4
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5 ; FUNC-LABEL: {{^}}rotr_i32:
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6 ; R600: BIT_ALIGN_INT
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7
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8 ; SI: v_alignbit_b32
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9 define amdgpu_kernel void @rotr_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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10 entry:
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11 %tmp0 = sub i32 32, %y
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12 %tmp1 = shl i32 %x, %tmp0
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13 %tmp2 = lshr i32 %x, %y
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14 %tmp3 = or i32 %tmp1, %tmp2
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15 store i32 %tmp3, i32 addrspace(1)* %in
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16 ret void
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17 }
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18
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19 ; FUNC-LABEL: {{^}}rotr_v2i32:
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20 ; R600: BIT_ALIGN_INT
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21 ; R600: BIT_ALIGN_INT
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22
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23 ; SI: v_alignbit_b32
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24 ; SI: v_alignbit_b32
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25 define amdgpu_kernel void @rotr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
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26 entry:
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27 %tmp0 = sub <2 x i32> <i32 32, i32 32>, %y
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28 %tmp1 = shl <2 x i32> %x, %tmp0
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29 %tmp2 = lshr <2 x i32> %x, %y
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30 %tmp3 = or <2 x i32> %tmp1, %tmp2
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31 store <2 x i32> %tmp3, <2 x i32> addrspace(1)* %in
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32 ret void
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33 }
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34
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35 ; FUNC-LABEL: {{^}}rotr_v4i32:
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36 ; R600: BIT_ALIGN_INT
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37 ; R600: BIT_ALIGN_INT
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38 ; R600: BIT_ALIGN_INT
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39 ; R600: BIT_ALIGN_INT
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40
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41 ; SI: v_alignbit_b32
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42 ; SI: v_alignbit_b32
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43 ; SI: v_alignbit_b32
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44 ; SI: v_alignbit_b32
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45 define amdgpu_kernel void @rotr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
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46 entry:
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47 %tmp0 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
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48 %tmp1 = shl <4 x i32> %x, %tmp0
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49 %tmp2 = lshr <4 x i32> %x, %y
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50 %tmp3 = or <4 x i32> %tmp1, %tmp2
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51 store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %in
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52 ret void
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53 }