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comparison llvm/test/CodeGen/AMDGPU/vselect.ll @ 252:1f2b6ac9f198 llvm-original

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LLVM16-1
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Fri, 18 Aug 2023 09:04:13 +0900
parents c4bab56944e8
children
comparison
equal deleted inserted replaced
237:c80f45b162ad 252:1f2b6ac9f198
15 ; SI-DAG: s_cmp_gt_i32 15 ; SI-DAG: s_cmp_gt_i32
16 ; SI-DAG: s_cselect_b32 16 ; SI-DAG: s_cselect_b32
17 ; SI-DAG: s_cmp_gt_i32 17 ; SI-DAG: s_cmp_gt_i32
18 ; SI-DAG: s_cselect_b32 18 ; SI-DAG: s_cselect_b32
19 19
20 define amdgpu_kernel void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1, <2 x i32> %val) { 20 define amdgpu_kernel void @test_select_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, <2 x i32> %val) {
21 entry: 21 entry:
22 %load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0 22 %load0 = load <2 x i32>, ptr addrspace(1) %in0
23 %load1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1 23 %load1 = load <2 x i32>, ptr addrspace(1) %in1
24 %cmp = icmp sgt <2 x i32> %load0, %load1 24 %cmp = icmp sgt <2 x i32> %load0, %load1
25 %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0 25 %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0
26 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 26 store <2 x i32> %result, ptr addrspace(1) %out
27 ret void 27 ret void
28 } 28 }
29 29
30 ; FUNC-LABEL: {{^}}test_select_v2f32: 30 ; FUNC-LABEL: {{^}}test_select_v2f32:
31 31
35 ; SI: v_cmp_neq_f32_e32 vcc 35 ; SI: v_cmp_neq_f32_e32 vcc
36 ; SI: v_cndmask_b32_e32 36 ; SI: v_cndmask_b32_e32
37 ; SI: v_cmp_neq_f32_e32 vcc 37 ; SI: v_cmp_neq_f32_e32 vcc
38 ; SI: v_cndmask_b32_e32 38 ; SI: v_cndmask_b32_e32
39 39
40 define amdgpu_kernel void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) { 40 define amdgpu_kernel void @test_select_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {
41 entry: 41 entry:
42 %0 = load <2 x float>, <2 x float> addrspace(1)* %in0 42 %0 = load <2 x float>, ptr addrspace(1) %in0
43 %1 = load <2 x float>, <2 x float> addrspace(1)* %in1 43 %1 = load <2 x float>, ptr addrspace(1) %in1
44 %cmp = fcmp une <2 x float> %0, %1 44 %cmp = fcmp une <2 x float> %0, %1
45 %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1 45 %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1
46 store <2 x float> %result, <2 x float> addrspace(1)* %out 46 store <2 x float> %result, ptr addrspace(1) %out
47 ret void 47 ret void
48 } 48 }
49 49
50 ;FUNC-LABEL: {{^}}test_select_v4i32: 50 ;FUNC-LABEL: {{^}}test_select_v4i32:
51 51
62 ; SI-DAG: s_cselect_b32 62 ; SI-DAG: s_cselect_b32
63 ; SI-DAG: s_cselect_b32 63 ; SI-DAG: s_cselect_b32
64 ; SI-DAG: s_cselect_b32 64 ; SI-DAG: s_cselect_b32
65 ; SI-DAG: s_cselect_b32 65 ; SI-DAG: s_cselect_b32
66 66
67 define amdgpu_kernel void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1, <4 x i32> %val) { 67 define amdgpu_kernel void @test_select_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, <4 x i32> %val) {
68 entry: 68 entry:
69 %load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0 69 %load0 = load <4 x i32>, ptr addrspace(1) %in0
70 %load1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1 70 %load1 = load <4 x i32>, ptr addrspace(1) %in1
71 %cmp = icmp sgt <4 x i32> %load0, %load1 71 %cmp = icmp sgt <4 x i32> %load0, %load1
72 %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0 72 %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0
73 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 73 store <4 x i32> %result, ptr addrspace(1) %out
74 ret void 74 ret void
75 } 75 }
76 76
77 ;FUNC-LABEL: {{^}}test_select_v4f32: 77 ;FUNC-LABEL: {{^}}test_select_v4f32:
78 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 78 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
82 82
83 ; SI: v_cndmask_b32_e32 83 ; SI: v_cndmask_b32_e32
84 ; SI: v_cndmask_b32_e32 84 ; SI: v_cndmask_b32_e32
85 ; SI: v_cndmask_b32_e32 85 ; SI: v_cndmask_b32_e32
86 ; SI: v_cndmask_b32_e32 86 ; SI: v_cndmask_b32_e32
87 define amdgpu_kernel void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) { 87 define amdgpu_kernel void @test_select_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {
88 entry: 88 entry:
89 %0 = load <4 x float>, <4 x float> addrspace(1)* %in0 89 %0 = load <4 x float>, ptr addrspace(1) %in0
90 %1 = load <4 x float>, <4 x float> addrspace(1)* %in1 90 %1 = load <4 x float>, ptr addrspace(1) %in1
91 %cmp = fcmp une <4 x float> %0, %1 91 %cmp = fcmp une <4 x float> %0, %1
92 %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1 92 %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1
93 store <4 x float> %result, <4 x float> addrspace(1)* %out 93 store <4 x float> %result, ptr addrspace(1) %out
94 ret void 94 ret void
95 } 95 }