--- a/llvm/test/CodeGen/AMDGPU/vselect.ll	Wed Nov 09 17:47:54 2022 +0900
+++ b/llvm/test/CodeGen/AMDGPU/vselect.ll	Fri Aug 18 09:04:13 2023 +0900
@@ -17,13 +17,13 @@
 ; SI-DAG: s_cmp_gt_i32
 ; SI-DAG: s_cselect_b32
 
-define amdgpu_kernel void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1, <2 x i32> %val) {
+define amdgpu_kernel void @test_select_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, <2 x i32> %val) {
 entry:
-  %load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0
-  %load1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1
+  %load0 = load <2 x i32>, ptr addrspace(1) %in0
+  %load1 = load <2 x i32>, ptr addrspace(1) %in1
   %cmp = icmp sgt <2 x i32> %load0, %load1
   %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0
-  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  store <2 x i32> %result, ptr addrspace(1) %out
   ret void
 }
 
@@ -37,13 +37,13 @@
 ; SI: v_cmp_neq_f32_e32 vcc
 ; SI: v_cndmask_b32_e32
 
-define amdgpu_kernel void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) {
+define amdgpu_kernel void @test_select_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {
 entry:
-  %0 = load <2 x float>, <2 x float> addrspace(1)* %in0
-  %1 = load <2 x float>, <2 x float> addrspace(1)* %in1
+  %0 = load <2 x float>, ptr addrspace(1) %in0
+  %1 = load <2 x float>, ptr addrspace(1) %in1
   %cmp = fcmp une <2 x float> %0, %1
   %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1
-  store <2 x float> %result, <2 x float> addrspace(1)* %out
+  store <2 x float> %result, ptr addrspace(1) %out
   ret void
 }
 
@@ -64,13 +64,13 @@
 ; SI-DAG: s_cselect_b32
 ; SI-DAG: s_cselect_b32
 
-define amdgpu_kernel void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1, <4 x i32> %val) {
+define amdgpu_kernel void @test_select_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, <4 x i32> %val) {
 entry:
-  %load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0
-  %load1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1
+  %load0 = load <4 x i32>, ptr addrspace(1) %in0
+  %load1 = load <4 x i32>, ptr addrspace(1) %in1
   %cmp = icmp sgt <4 x i32> %load0, %load1
   %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0
-  store <4 x i32> %result, <4 x i32> addrspace(1)* %out
+  store <4 x i32> %result, ptr addrspace(1) %out
   ret void
 }
 
@@ -84,12 +84,12 @@
 ; SI: v_cndmask_b32_e32
 ; SI: v_cndmask_b32_e32
 ; SI: v_cndmask_b32_e32
-define amdgpu_kernel void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) {
+define amdgpu_kernel void @test_select_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {
 entry:
-  %0 = load <4 x float>, <4 x float> addrspace(1)* %in0
-  %1 = load <4 x float>, <4 x float> addrspace(1)* %in1
+  %0 = load <4 x float>, ptr addrspace(1) %in0
+  %1 = load <4 x float>, ptr addrspace(1) %in1
   %cmp = fcmp une <4 x float> %0, %1
   %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1
-  store <4 x float> %result, <4 x float> addrspace(1)* %out
+  store <4 x float> %result, ptr addrspace(1) %out
   ret void
 }