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comparison llvm/test/Transforms/IndVarSimplify/elim-extend.ll @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 0572611fdcc8
children c4bab56944e8
comparison
equal deleted inserted replaced
173:0572611fdcc8 207:2e18cbf3894f
6 ; IV with constant start, preinc and postinc sign extends, with and without NSW. 6 ; IV with constant start, preinc and postinc sign extends, with and without NSW.
7 ; IV rewrite only removes one sext. WidenIVs removes all three. 7 ; IV rewrite only removes one sext. WidenIVs removes all three.
8 define void @postincConstIV(i8* %base, i32 %limit) nounwind { 8 define void @postincConstIV(i8* %base, i32 %limit) nounwind {
9 ; CHECK-LABEL: @postincConstIV( 9 ; CHECK-LABEL: @postincConstIV(
10 ; CHECK-NEXT: entry: 10 ; CHECK-NEXT: entry:
11 ; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i32 [[LIMIT:%.*]], 0 11 ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[LIMIT:%.*]], i32 0)
12 ; CHECK-NEXT: [[SMAX:%.*]] = select i1 [[TMP0]], i32 [[LIMIT]], i32 0 12 ; CHECK-NEXT: [[TMP0:%.*]] = add nuw i32 [[SMAX]], 1
13 ; CHECK-NEXT: [[TMP1:%.*]] = add nuw i32 [[SMAX]], 1 13 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TMP0]] to i64
14 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TMP1]] to i64
15 ; CHECK-NEXT: br label [[LOOP:%.*]] 14 ; CHECK-NEXT: br label [[LOOP:%.*]]
16 ; CHECK: loop: 15 ; CHECK: loop:
17 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ] 16 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
18 ; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]] 17 ; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]]
19 ; CHECK-NEXT: store i8 0, i8* [[PREADR]] 18 ; CHECK-NEXT: store i8 0, i8* [[PREADR]], align 1
20 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 19 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
21 ; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]] 20 ; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
22 ; CHECK-NEXT: store i8 0, i8* [[POSTADR]] 21 ; CHECK-NEXT: store i8 0, i8* [[POSTADR]], align 1
23 ; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr inbounds i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]] 22 ; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr inbounds i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
24 ; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]] 23 ; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]], align 1
25 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] 24 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
26 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]] 25 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
27 ; CHECK: exit: 26 ; CHECK: exit:
28 ; CHECK-NEXT: br label [[RETURN:%.*]] 27 ; CHECK-NEXT: br label [[RETURN:%.*]]
29 ; CHECK: return: 28 ; CHECK: return:
66 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[LIMIT]] to i64 65 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[LIMIT]] to i64
67 ; CHECK-NEXT: br label [[LOOP:%.*]] 66 ; CHECK-NEXT: br label [[LOOP:%.*]]
68 ; CHECK: loop: 67 ; CHECK: loop:
69 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP0]], [[LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ] 68 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP0]], [[LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
70 ; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]] 69 ; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]]
71 ; CHECK-NEXT: store i8 0, i8* [[PREADR]] 70 ; CHECK-NEXT: store i8 0, i8* [[PREADR]], align 1
72 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1 71 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
73 ; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]] 72 ; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
74 ; CHECK-NEXT: store i8 0, i8* [[POSTADR]] 73 ; CHECK-NEXT: store i8 0, i8* [[POSTADR]], align 1
75 ; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]] 74 ; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
76 ; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]] 75 ; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]], align 1
77 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] 76 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
78 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]] 77 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
79 ; CHECK: exit: 78 ; CHECK: exit:
80 ; CHECK-NEXT: br label [[RETURN]] 79 ; CHECK-NEXT: br label [[RETURN]]
81 ; CHECK: return: 80 ; CHECK: return:
114 define void @nestedIV(i8* %address, i32 %limit) nounwind { 113 define void @nestedIV(i8* %address, i32 %limit) nounwind {
115 ; CHECK-LABEL: @nestedIV( 114 ; CHECK-LABEL: @nestedIV(
116 ; CHECK-NEXT: entry: 115 ; CHECK-NEXT: entry:
117 ; CHECK-NEXT: [[LIMITDEC:%.*]] = add i32 [[LIMIT:%.*]], -1 116 ; CHECK-NEXT: [[LIMITDEC:%.*]] = add i32 [[LIMIT:%.*]], -1
118 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[LIMITDEC]] to i64 117 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[LIMITDEC]] to i64
119 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[LIMIT]], 1 118 ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[LIMIT]], i32 1)
120 ; CHECK-NEXT: [[SMAX:%.*]] = select i1 [[TMP1]], i32 [[LIMIT]], i32 1
121 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64 119 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
122 ; CHECK-NEXT: br label [[OUTERLOOP:%.*]] 120 ; CHECK-NEXT: br label [[OUTERLOOP:%.*]]
123 ; CHECK: outerloop: 121 ; CHECK: outerloop:
124 ; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], [[OUTERMERGE:%.*]] ], [ 0, [[ENTRY:%.*]] ] 122 ; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], [[OUTERMERGE:%.*]] ], [ 0, [[ENTRY:%.*]] ]
125 ; CHECK-NEXT: [[INNERCOUNT:%.*]] = phi i32 [ [[INNERCOUNT_MERGE:%.*]], [[OUTERMERGE]] ], [ 0, [[ENTRY]] ] 123 ; CHECK-NEXT: [[INNERCOUNT:%.*]] = phi i32 [ [[INNERCOUNT_MERGE:%.*]], [[OUTERMERGE]] ], [ 0, [[ENTRY]] ]
126 ; CHECK-NEXT: [[TMP2:%.*]] = add nsw i64 [[INDVARS_IV1]], -1 124 ; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
127 ; CHECK-NEXT: [[ADR1:%.*]] = getelementptr i8, i8* [[ADDRESS:%.*]], i64 [[TMP2]] 125 ; CHECK-NEXT: [[ADR1:%.*]] = getelementptr i8, i8* [[ADDRESS:%.*]], i64 [[TMP1]]
128 ; CHECK-NEXT: store i8 0, i8* [[ADR1]] 126 ; CHECK-NEXT: store i8 0, i8* [[ADR1]], align 1
129 ; CHECK-NEXT: br label [[INNERPREHEADER:%.*]] 127 ; CHECK-NEXT: br label [[INNERPREHEADER:%.*]]
130 ; CHECK: innerpreheader: 128 ; CHECK: innerpreheader:
131 ; CHECK-NEXT: [[INNERPRECMP:%.*]] = icmp sgt i32 [[LIMITDEC]], [[INNERCOUNT]] 129 ; CHECK-NEXT: [[INNERPRECMP:%.*]] = icmp sgt i32 [[LIMITDEC]], [[INNERCOUNT]]
132 ; CHECK-NEXT: br i1 [[INNERPRECMP]], label [[INNERLOOP_PREHEADER:%.*]], label [[OUTERMERGE]] 130 ; CHECK-NEXT: br i1 [[INNERPRECMP]], label [[INNERLOOP_PREHEADER:%.*]], label [[OUTERMERGE]]
133 ; CHECK: innerloop.preheader: 131 ; CHECK: innerloop.preheader:
134 ; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[INNERCOUNT]] to i64 132 ; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[INNERCOUNT]] to i64
135 ; CHECK-NEXT: br label [[INNERLOOP:%.*]] 133 ; CHECK-NEXT: br label [[INNERLOOP:%.*]]
136 ; CHECK: innerloop: 134 ; CHECK: innerloop:
137 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP3]], [[INNERLOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[INNERLOOP]] ] 135 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP2]], [[INNERLOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[INNERLOOP]] ]
138 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1 136 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
139 ; CHECK-NEXT: [[ADR2:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV]] 137 ; CHECK-NEXT: [[ADR2:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV]]
140 ; CHECK-NEXT: store i8 0, i8* [[ADR2]] 138 ; CHECK-NEXT: store i8 0, i8* [[ADR2]], align 1
141 ; CHECK-NEXT: [[ADR3:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV_NEXT]] 139 ; CHECK-NEXT: [[ADR3:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV_NEXT]]
142 ; CHECK-NEXT: store i8 0, i8* [[ADR3]] 140 ; CHECK-NEXT: store i8 0, i8* [[ADR3]], align 1
143 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[TMP0]] 141 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[TMP0]]
144 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[INNERLOOP]], label [[INNEREXIT:%.*]] 142 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[INNERLOOP]], label [[INNEREXIT:%.*]]
145 ; CHECK: innerexit: 143 ; CHECK: innerexit:
146 ; CHECK-NEXT: [[INNERCOUNT_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV_NEXT]], [[INNERLOOP]] ] 144 ; CHECK-NEXT: [[INNERCOUNT_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV_NEXT]], [[INNERLOOP]] ]
147 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[INNERCOUNT_LCSSA_WIDE]] to i32 145 ; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INNERCOUNT_LCSSA_WIDE]] to i32
148 ; CHECK-NEXT: br label [[OUTERMERGE]] 146 ; CHECK-NEXT: br label [[OUTERMERGE]]
149 ; CHECK: outermerge: 147 ; CHECK: outermerge:
150 ; CHECK-NEXT: [[INNERCOUNT_MERGE]] = phi i32 [ [[TMP4]], [[INNEREXIT]] ], [ [[INNERCOUNT]], [[INNERPREHEADER]] ] 148 ; CHECK-NEXT: [[INNERCOUNT_MERGE]] = phi i32 [ [[TMP3]], [[INNEREXIT]] ], [ [[INNERCOUNT]], [[INNERPREHEADER]] ]
151 ; CHECK-NEXT: [[ADR4:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV1]] 149 ; CHECK-NEXT: [[ADR4:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV1]]
152 ; CHECK-NEXT: store i8 0, i8* [[ADR4]] 150 ; CHECK-NEXT: store i8 0, i8* [[ADR4]], align 1
153 ; CHECK-NEXT: [[OFS5:%.*]] = sext i32 [[INNERCOUNT_MERGE]] to i64 151 ; CHECK-NEXT: [[OFS5:%.*]] = sext i32 [[INNERCOUNT_MERGE]] to i64
154 ; CHECK-NEXT: [[ADR5:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[OFS5]] 152 ; CHECK-NEXT: [[ADR5:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[OFS5]]
155 ; CHECK-NEXT: store i8 0, i8* [[ADR5]] 153 ; CHECK-NEXT: store i8 0, i8* [[ADR5]], align 1
156 ; CHECK-NEXT: [[INDVARS_IV_NEXT2]] = add nuw nsw i64 [[INDVARS_IV1]], 1 154 ; CHECK-NEXT: [[INDVARS_IV_NEXT2]] = add nuw nsw i64 [[INDVARS_IV1]], 1
157 ; CHECK-NEXT: [[EXITCOND4:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT2]], [[WIDE_TRIP_COUNT]] 155 ; CHECK-NEXT: [[EXITCOND4:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT2]], [[WIDE_TRIP_COUNT]]
158 ; CHECK-NEXT: br i1 [[EXITCOND4]], label [[OUTERLOOP]], label [[RETURN:%.*]] 156 ; CHECK-NEXT: br i1 [[EXITCOND4]], label [[OUTERLOOP]], label [[RETURN:%.*]]
159 ; CHECK: return: 157 ; CHECK: return:
160 ; CHECK-NEXT: ret void 158 ; CHECK-NEXT: ret void