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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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2 ; RUN: opt < %s -indvars -S | FileCheck %s
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3
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4 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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5
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6 ; IV with constant start, preinc and postinc sign extends, with and without NSW.
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7 ; IV rewrite only removes one sext. WidenIVs removes all three.
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8 define void @postincConstIV(i8* %base, i32 %limit) nounwind {
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9 ; CHECK-LABEL: @postincConstIV(
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10 ; CHECK-NEXT: entry:
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207
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11 ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[LIMIT:%.*]], i32 0)
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12 ; CHECK-NEXT: [[TMP0:%.*]] = add nuw i32 [[SMAX]], 1
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13 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TMP0]] to i64
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150
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14 ; CHECK-NEXT: br label [[LOOP:%.*]]
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15 ; CHECK: loop:
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16 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
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17 ; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]]
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207
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18 ; CHECK-NEXT: store i8 0, i8* [[PREADR]], align 1
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150
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19 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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20 ; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
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207
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21 ; CHECK-NEXT: store i8 0, i8* [[POSTADR]], align 1
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150
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22 ; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr inbounds i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
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207
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23 ; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]], align 1
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173
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24 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
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25 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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150
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26 ; CHECK: exit:
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27 ; CHECK-NEXT: br label [[RETURN:%.*]]
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28 ; CHECK: return:
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29 ; CHECK-NEXT: ret void
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30 ;
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31 entry:
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32 br label %loop
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33 loop:
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34 %iv = phi i32 [ %postiv, %loop ], [ 0, %entry ]
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35 %ivnsw = phi i32 [ %postivnsw, %loop ], [ 0, %entry ]
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36 %preofs = sext i32 %iv to i64
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37 %preadr = getelementptr i8, i8* %base, i64 %preofs
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38 store i8 0, i8* %preadr
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39 %postiv = add i32 %iv, 1
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40 %postofs = sext i32 %postiv to i64
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41 %postadr = getelementptr i8, i8* %base, i64 %postofs
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42 store i8 0, i8* %postadr
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43 %postivnsw = add nsw i32 %ivnsw, 1
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44 %postofsnsw = sext i32 %postivnsw to i64
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45 %postadrnsw = getelementptr inbounds i8, i8* %base, i64 %postofsnsw
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46 store i8 0, i8* %postadrnsw
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47 %cond = icmp sgt i32 %limit, %iv
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48 br i1 %cond, label %loop, label %exit
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49 exit:
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50 br label %return
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51 return:
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52 ret void
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53 }
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54
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55 ; IV with nonconstant start, preinc and postinc sign extends,
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56 ; with and without NSW.
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57 ; As with postincConstIV, WidenIVs removes all three sexts.
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58 define void @postincVarIV(i8* %base, i32 %init, i32 %limit) nounwind {
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59 ; CHECK-LABEL: @postincVarIV(
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60 ; CHECK-NEXT: entry:
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61 ; CHECK-NEXT: [[PRECOND:%.*]] = icmp sgt i32 [[LIMIT:%.*]], [[INIT:%.*]]
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62 ; CHECK-NEXT: br i1 [[PRECOND]], label [[LOOP_PREHEADER:%.*]], label [[RETURN:%.*]]
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63 ; CHECK: loop.preheader:
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64 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[INIT]] to i64
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65 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = sext i32 [[LIMIT]] to i64
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66 ; CHECK-NEXT: br label [[LOOP:%.*]]
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67 ; CHECK: loop:
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68 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP0]], [[LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
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69 ; CHECK-NEXT: [[PREADR:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i64 [[INDVARS_IV]]
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207
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70 ; CHECK-NEXT: store i8 0, i8* [[PREADR]], align 1
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150
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71 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
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72 ; CHECK-NEXT: [[POSTADR:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
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207
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73 ; CHECK-NEXT: store i8 0, i8* [[POSTADR]], align 1
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150
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74 ; CHECK-NEXT: [[POSTADRNSW:%.*]] = getelementptr i8, i8* [[BASE]], i64 [[INDVARS_IV_NEXT]]
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207
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75 ; CHECK-NEXT: store i8 0, i8* [[POSTADRNSW]], align 1
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150
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76 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
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77 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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78 ; CHECK: exit:
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79 ; CHECK-NEXT: br label [[RETURN]]
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80 ; CHECK: return:
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81 ; CHECK-NEXT: ret void
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82 ;
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83 entry:
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84 %precond = icmp sgt i32 %limit, %init
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85 br i1 %precond, label %loop, label %return
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86 loop:
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87 %iv = phi i32 [ %postiv, %loop ], [ %init, %entry ]
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88 %ivnsw = phi i32 [ %postivnsw, %loop ], [ %init, %entry ]
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89 %preofs = sext i32 %iv to i64
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90 %preadr = getelementptr i8, i8* %base, i64 %preofs
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91 store i8 0, i8* %preadr
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92 %postiv = add i32 %iv, 1
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93 %postofs = sext i32 %postiv to i64
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94 %postadr = getelementptr i8, i8* %base, i64 %postofs
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95 store i8 0, i8* %postadr
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96 %postivnsw = add nsw i32 %ivnsw, 1
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97 %postofsnsw = sext i32 %postivnsw to i64
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98 %postadrnsw = getelementptr i8, i8* %base, i64 %postofsnsw
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99 store i8 0, i8* %postadrnsw
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100 %cond = icmp sgt i32 %limit, %postiv
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101 br i1 %cond, label %loop, label %exit
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102 exit:
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103 br label %return
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104 return:
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105 ret void
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106 }
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107
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108 ; Test sign extend elimination in the inner and outer loop.
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109 ; %outercount is straightforward to widen, besides being in an outer loop.
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110 ; %innercount is currently blocked by lcssa, so is not widened.
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111 ; %inneriv can be widened only after proving it has no signed-overflow
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112 ; based on the loop test.
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113 define void @nestedIV(i8* %address, i32 %limit) nounwind {
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114 ; CHECK-LABEL: @nestedIV(
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115 ; CHECK-NEXT: entry:
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116 ; CHECK-NEXT: [[LIMITDEC:%.*]] = add i32 [[LIMIT:%.*]], -1
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117 ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[LIMITDEC]] to i64
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207
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118 ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[LIMIT]], i32 1)
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173
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119 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SMAX]] to i64
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150
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120 ; CHECK-NEXT: br label [[OUTERLOOP:%.*]]
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121 ; CHECK: outerloop:
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122 ; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], [[OUTERMERGE:%.*]] ], [ 0, [[ENTRY:%.*]] ]
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123 ; CHECK-NEXT: [[INNERCOUNT:%.*]] = phi i32 [ [[INNERCOUNT_MERGE:%.*]], [[OUTERMERGE]] ], [ 0, [[ENTRY]] ]
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207
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124 ; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
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125 ; CHECK-NEXT: [[ADR1:%.*]] = getelementptr i8, i8* [[ADDRESS:%.*]], i64 [[TMP1]]
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126 ; CHECK-NEXT: store i8 0, i8* [[ADR1]], align 1
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150
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127 ; CHECK-NEXT: br label [[INNERPREHEADER:%.*]]
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128 ; CHECK: innerpreheader:
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129 ; CHECK-NEXT: [[INNERPRECMP:%.*]] = icmp sgt i32 [[LIMITDEC]], [[INNERCOUNT]]
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130 ; CHECK-NEXT: br i1 [[INNERPRECMP]], label [[INNERLOOP_PREHEADER:%.*]], label [[OUTERMERGE]]
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131 ; CHECK: innerloop.preheader:
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207
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132 ; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[INNERCOUNT]] to i64
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150
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133 ; CHECK-NEXT: br label [[INNERLOOP:%.*]]
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134 ; CHECK: innerloop:
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207
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135 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP2]], [[INNERLOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[INNERLOOP]] ]
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150
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136 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
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137 ; CHECK-NEXT: [[ADR2:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV]]
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207
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138 ; CHECK-NEXT: store i8 0, i8* [[ADR2]], align 1
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150
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139 ; CHECK-NEXT: [[ADR3:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV_NEXT]]
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207
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140 ; CHECK-NEXT: store i8 0, i8* [[ADR3]], align 1
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150
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141 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[TMP0]]
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142 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[INNERLOOP]], label [[INNEREXIT:%.*]]
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143 ; CHECK: innerexit:
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144 ; CHECK-NEXT: [[INNERCOUNT_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV_NEXT]], [[INNERLOOP]] ]
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207
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145 ; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INNERCOUNT_LCSSA_WIDE]] to i32
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150
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146 ; CHECK-NEXT: br label [[OUTERMERGE]]
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147 ; CHECK: outermerge:
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207
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148 ; CHECK-NEXT: [[INNERCOUNT_MERGE]] = phi i32 [ [[TMP3]], [[INNEREXIT]] ], [ [[INNERCOUNT]], [[INNERPREHEADER]] ]
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150
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149 ; CHECK-NEXT: [[ADR4:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV1]]
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207
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150 ; CHECK-NEXT: store i8 0, i8* [[ADR4]], align 1
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150
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151 ; CHECK-NEXT: [[OFS5:%.*]] = sext i32 [[INNERCOUNT_MERGE]] to i64
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152 ; CHECK-NEXT: [[ADR5:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[OFS5]]
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207
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153 ; CHECK-NEXT: store i8 0, i8* [[ADR5]], align 1
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150
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154 ; CHECK-NEXT: [[INDVARS_IV_NEXT2]] = add nuw nsw i64 [[INDVARS_IV1]], 1
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173
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155 ; CHECK-NEXT: [[EXITCOND4:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT2]], [[WIDE_TRIP_COUNT]]
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156 ; CHECK-NEXT: br i1 [[EXITCOND4]], label [[OUTERLOOP]], label [[RETURN:%.*]]
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150
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157 ; CHECK: return:
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158 ; CHECK-NEXT: ret void
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159 ;
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160 entry:
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161 %limitdec = add i32 %limit, -1
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162 br label %outerloop
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163
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164 ; Eliminate %ofs1 after widening outercount.
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165 ; IV rewriting hoists a gep into this block. We don't like that.
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166 outerloop:
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167 %outercount = phi i32 [ %outerpostcount, %outermerge ], [ 0, %entry ]
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168 %innercount = phi i32 [ %innercount.merge, %outermerge ], [ 0, %entry ]
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169
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170 %outercountdec = add i32 %outercount, -1
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171 %ofs1 = sext i32 %outercountdec to i64
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172 %adr1 = getelementptr i8, i8* %address, i64 %ofs1
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173 store i8 0, i8* %adr1
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174
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175 br label %innerpreheader
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176
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177 innerpreheader:
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178 %innerprecmp = icmp sgt i32 %limitdec, %innercount
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179 br i1 %innerprecmp, label %innerloop, label %outermerge
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180
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181 ; Eliminate %ofs2 after widening inneriv.
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182 ; Eliminate %ofs3 after normalizing sext(innerpostiv)
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183 ; FIXME: We should check that indvars does not increase the number of
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184 ; IVs in this loop. sext elimination plus LFTR currently results in 2 final
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185 ; IVs. Waiting to remove LFTR.
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186 innerloop:
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187 %inneriv = phi i32 [ %innerpostiv, %innerloop ], [ %innercount, %innerpreheader ]
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188 %innerpostiv = add i32 %inneriv, 1
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189
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190 %ofs2 = sext i32 %inneriv to i64
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191 %adr2 = getelementptr i8, i8* %address, i64 %ofs2
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192 store i8 0, i8* %adr2
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193
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194 %ofs3 = sext i32 %innerpostiv to i64
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195 %adr3 = getelementptr i8, i8* %address, i64 %ofs3
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196 store i8 0, i8* %adr3
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197
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198 %innercmp = icmp sgt i32 %limitdec, %innerpostiv
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199 br i1 %innercmp, label %innerloop, label %innerexit
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200
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201 innerexit:
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202 %innercount.lcssa = phi i32 [ %innerpostiv, %innerloop ]
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203 br label %outermerge
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204
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205 ; Eliminate %ofs4 after widening outercount
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206 ; TODO: Eliminate %ofs5 after removing lcssa
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207 outermerge:
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208 %innercount.merge = phi i32 [ %innercount.lcssa, %innerexit ], [ %innercount, %innerpreheader ]
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209
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210 %ofs4 = sext i32 %outercount to i64
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211 %adr4 = getelementptr i8, i8* %address, i64 %ofs4
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212 store i8 0, i8* %adr4
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213
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214 %ofs5 = sext i32 %innercount.merge to i64
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215 %adr5 = getelementptr i8, i8* %address, i64 %ofs5
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216 store i8 0, i8* %adr5
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217
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218 %outerpostcount = add i32 %outercount, 1
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219 %tmp47 = icmp slt i32 %outerpostcount, %limit
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220 br i1 %tmp47, label %outerloop, label %return
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221
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222 return:
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223 ret void
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224 }
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