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comparison lib/CodeGen/LiveRegMatrix.cpp @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
comparison
equal deleted inserted replaced
133:c60214abe0e8 134:3a76565eade5
13 13
14 #include "llvm/CodeGen/LiveRegMatrix.h" 14 #include "llvm/CodeGen/LiveRegMatrix.h"
15 #include "RegisterCoalescer.h" 15 #include "RegisterCoalescer.h"
16 #include "llvm/ADT/Statistic.h" 16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/LiveInterval.h" 17 #include "llvm/CodeGen/LiveInterval.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveIntervalUnion.h" 18 #include "llvm/CodeGen/LiveIntervalUnion.h"
19 #include "llvm/CodeGen/LiveIntervals.h"
20 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/TargetRegisterInfo.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
21 #include "llvm/CodeGen/VirtRegMap.h" 23 #include "llvm/CodeGen/VirtRegMap.h"
22 #include "llvm/MC/LaneBitmask.h" 24 #include "llvm/MC/LaneBitmask.h"
23 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Pass.h" 26 #include "llvm/Pass.h"
25 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/raw_ostream.h" 28 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 #include <cassert> 29 #include <cassert>
30 30
31 using namespace llvm; 31 using namespace llvm;
32 32
33 #define DEBUG_TYPE "regalloc" 33 #define DEBUG_TYPE "regalloc"
100 } 100 }
101 return false; 101 return false;
102 } 102 }
103 103
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { 104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
105 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 105 DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI)
106 << " to " << PrintReg(PhysReg, TRI) << ':'); 106 << " to " << printReg(PhysReg, TRI) << ':');
107 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); 107 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
109 109
110 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, 110 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
111 const LiveRange &Range) { 111 const LiveRange &Range) {
112 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); 112 DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
113 Matrix[Unit].unify(VirtReg, Range); 113 Matrix[Unit].unify(VirtReg, Range);
114 return false; 114 return false;
115 }); 115 });
116 116
117 ++NumAssigned; 117 ++NumAssigned;
118 DEBUG(dbgs() << '\n'); 118 DEBUG(dbgs() << '\n');
119 } 119 }
120 120
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { 121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
122 unsigned PhysReg = VRM->getPhys(VirtReg.reg); 122 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
123 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) 123 DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI)
124 << " from " << PrintReg(PhysReg, TRI) << ':'); 124 << " from " << printReg(PhysReg, TRI) << ':');
125 VRM->clearVirt(VirtReg.reg); 125 VRM->clearVirt(VirtReg.reg);
126 126
127 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, 127 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
128 const LiveRange &Range) { 128 const LiveRange &Range) {
129 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI)); 129 DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI));
130 Matrix[Unit].extract(VirtReg, Range); 130 Matrix[Unit].extract(VirtReg, Range);
131 return false; 131 return false;
132 }); 132 });
133 133
134 ++NumUnassigned; 134 ++NumUnassigned;
203 if (Interference) 203 if (Interference)
204 return IK_VirtReg; 204 return IK_VirtReg;
205 205
206 return IK_Free; 206 return IK_Free;
207 } 207 }
208
209 bool LiveRegMatrix::checkInterference(SlotIndex Start, SlotIndex End,
210 unsigned PhysReg) {
211 // Construct artificial live range containing only one segment [Start, End).
212 VNInfo valno(0, Start);
213 LiveRange::Segment Seg(Start, End, &valno);
214 LiveRange LR;
215 LR.addSegment(Seg);
216
217 // Check for interference with that segment
218 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
219 if (query(LR, *Units).checkInterference())
220 return true;
221 }
222 return false;
223 }