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annotate lib/CodeGen/LiveRegMatrix.cpp @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
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1 //===- LiveRegMatrix.cpp - Track register interference --------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the LiveRegMatrix analysis pass.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "llvm/CodeGen/LiveRegMatrix.h"
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15 #include "RegisterCoalescer.h"
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16 #include "llvm/ADT/Statistic.h"
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17 #include "llvm/CodeGen/LiveInterval.h"
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18 #include "llvm/CodeGen/LiveIntervalUnion.h"
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19 #include "llvm/CodeGen/LiveIntervals.h"
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20 #include "llvm/CodeGen/MachineFunction.h"
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21 #include "llvm/CodeGen/TargetRegisterInfo.h"
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22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
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23 #include "llvm/CodeGen/VirtRegMap.h"
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24 #include "llvm/MC/LaneBitmask.h"
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25 #include "llvm/MC/MCRegisterInfo.h"
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26 #include "llvm/Pass.h"
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27 #include "llvm/Support/Debug.h"
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28 #include "llvm/Support/raw_ostream.h"
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29 #include <cassert>
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30
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31 using namespace llvm;
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32
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33 #define DEBUG_TYPE "regalloc"
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34
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35 STATISTIC(NumAssigned , "Number of registers assigned");
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36 STATISTIC(NumUnassigned , "Number of registers unassigned");
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37
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38 char LiveRegMatrix::ID = 0;
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39 INITIALIZE_PASS_BEGIN(LiveRegMatrix, "liveregmatrix",
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40 "Live Register Matrix", false, false)
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41 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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42 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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43 INITIALIZE_PASS_END(LiveRegMatrix, "liveregmatrix",
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44 "Live Register Matrix", false, false)
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45
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46 LiveRegMatrix::LiveRegMatrix() : MachineFunctionPass(ID) {}
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47
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48 void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const {
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49 AU.setPreservesAll();
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50 AU.addRequiredTransitive<LiveIntervals>();
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51 AU.addRequiredTransitive<VirtRegMap>();
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52 MachineFunctionPass::getAnalysisUsage(AU);
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53 }
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54
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55 bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
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56 TRI = MF.getSubtarget().getRegisterInfo();
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57 LIS = &getAnalysis<LiveIntervals>();
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58 VRM = &getAnalysis<VirtRegMap>();
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59
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60 unsigned NumRegUnits = TRI->getNumRegUnits();
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61 if (NumRegUnits != Matrix.size())
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62 Queries.reset(new LiveIntervalUnion::Query[NumRegUnits]);
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63 Matrix.init(LIUAlloc, NumRegUnits);
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64
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65 // Make sure no stale queries get reused.
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66 invalidateVirtRegs();
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67 return false;
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68 }
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69
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70 void LiveRegMatrix::releaseMemory() {
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71 for (unsigned i = 0, e = Matrix.size(); i != e; ++i) {
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72 Matrix[i].clear();
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73 // No need to clear Queries here, since LiveIntervalUnion::Query doesn't
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74 // have anything important to clear and LiveRegMatrix's runOnFunction()
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75 // does a std::unique_ptr::reset anyways.
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76 }
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77 }
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78
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79 template <typename Callable>
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80 static bool foreachUnit(const TargetRegisterInfo *TRI,
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81 LiveInterval &VRegInterval, unsigned PhysReg,
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82 Callable Func) {
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83 if (VRegInterval.hasSubRanges()) {
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84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
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85 unsigned Unit = (*Units).first;
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86 LaneBitmask Mask = (*Units).second;
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87 for (LiveInterval::SubRange &S : VRegInterval.subranges()) {
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88 if ((S.LaneMask & Mask).any()) {
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89 if (Func(Unit, S))
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90 return true;
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91 break;
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92 }
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93 }
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94 }
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95 } else {
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96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
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97 if (Func(*Units, VRegInterval))
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98 return true;
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99 }
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100 }
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101 return false;
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102 }
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103
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104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
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105 DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI)
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106 << " to " << printReg(PhysReg, TRI) << ':');
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107 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
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108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
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109
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110 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
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111 const LiveRange &Range) {
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112 DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
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113 Matrix[Unit].unify(VirtReg, Range);
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114 return false;
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115 });
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116
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117 ++NumAssigned;
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118 DEBUG(dbgs() << '\n');
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119 }
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120
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121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
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122 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
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123 DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI)
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124 << " from " << printReg(PhysReg, TRI) << ':');
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125 VRM->clearVirt(VirtReg.reg);
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126
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127 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
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128 const LiveRange &Range) {
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129 DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI));
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130 Matrix[Unit].extract(VirtReg, Range);
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131 return false;
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132 });
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133
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134 ++NumUnassigned;
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135 DEBUG(dbgs() << '\n');
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136 }
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137
95
afa8332a0e37 LLVM 3.8
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diff changeset
138 bool LiveRegMatrix::isPhysRegUsed(unsigned PhysReg) const {
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diff changeset
139 for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
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140 if (!Matrix[*Unit].empty())
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141 return true;
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142 }
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143 return false;
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144 }
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145
0
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146 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg,
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147 unsigned PhysReg) {
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148 // Check if the cached information is valid.
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149 // The same BitVector can be reused for all PhysRegs.
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150 // We could cache multiple VirtRegs if it becomes necessary.
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151 if (RegMaskVirtReg != VirtReg.reg || RegMaskTag != UserTag) {
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152 RegMaskVirtReg = VirtReg.reg;
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153 RegMaskTag = UserTag;
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154 RegMaskUsable.clear();
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155 LIS->checkRegMaskInterference(VirtReg, RegMaskUsable);
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156 }
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157
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158 // The BitVector is indexed by PhysReg, not register unit.
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159 // Regmask interference is more fine grained than regunits.
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160 // For example, a Win64 call can clobber %ymm8 yet preserve %xmm8.
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161 return !RegMaskUsable.empty() && (!PhysReg || !RegMaskUsable.test(PhysReg));
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162 }
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163
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164 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg,
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165 unsigned PhysReg) {
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166 if (VirtReg.empty())
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167 return false;
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168 CoalescerPair CP(VirtReg.reg, PhysReg, *TRI);
83
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169
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170 bool Result = foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
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171 const LiveRange &Range) {
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172 const LiveRange &UnitRange = LIS->getRegUnit(Unit);
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parents: 77
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173 return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes());
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174 });
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175 return Result;
0
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176 }
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177
121
803732b1fca8 LLVM 5.0
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diff changeset
178 LiveIntervalUnion::Query &LiveRegMatrix::query(const LiveRange &LR,
0
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diff changeset
179 unsigned RegUnit) {
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diff changeset
180 LiveIntervalUnion::Query &Q = Queries[RegUnit];
121
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diff changeset
181 Q.init(UserTag, LR, Matrix[RegUnit]);
0
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182 return Q;
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183 }
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184
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185 LiveRegMatrix::InterferenceKind
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diff changeset
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) {
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diff changeset
187 if (VirtReg.empty())
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diff changeset
188 return IK_Free;
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diff changeset
189
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190 // Regmask interference is the fastest check.
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diff changeset
191 if (checkRegMaskInterference(VirtReg, PhysReg))
95c75e76d11b LLVM 3.4
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diff changeset
192 return IK_RegMask;
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parents:
diff changeset
193
95c75e76d11b LLVM 3.4
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diff changeset
194 // Check for fixed interference.
95c75e76d11b LLVM 3.4
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diff changeset
195 if (checkRegUnitInterference(VirtReg, PhysReg))
95c75e76d11b LLVM 3.4
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diff changeset
196 return IK_RegUnit;
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parents:
diff changeset
197
95c75e76d11b LLVM 3.4
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diff changeset
198 // Check the matrix for virtual register interference.
121
803732b1fca8 LLVM 5.0
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parents: 120
diff changeset
199 bool Interference = foreachUnit(TRI, VirtReg, PhysReg,
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
200 [&](unsigned Unit, const LiveRange &LR) {
803732b1fca8 LLVM 5.0
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parents: 120
diff changeset
201 return query(LR, Unit).checkInterference();
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
202 });
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
203 if (Interference)
803732b1fca8 LLVM 5.0
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parents: 120
diff changeset
204 return IK_VirtReg;
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
205
95c75e76d11b LLVM 3.4
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parents:
diff changeset
206 return IK_Free;
95c75e76d11b LLVM 3.4
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parents:
diff changeset
207 }
134
3a76565eade5 update 5.0.1
mir3636
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diff changeset
208
3a76565eade5 update 5.0.1
mir3636
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diff changeset
209 bool LiveRegMatrix::checkInterference(SlotIndex Start, SlotIndex End,
3a76565eade5 update 5.0.1
mir3636
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diff changeset
210 unsigned PhysReg) {
3a76565eade5 update 5.0.1
mir3636
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diff changeset
211 // Construct artificial live range containing only one segment [Start, End).
3a76565eade5 update 5.0.1
mir3636
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diff changeset
212 VNInfo valno(0, Start);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
213 LiveRange::Segment Seg(Start, End, &valno);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
214 LiveRange LR;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
215 LR.addSegment(Seg);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
216
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
217 // Check for interference with that segment
3a76565eade5 update 5.0.1
mir3636
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diff changeset
218 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
219 if (query(LR, *Units).checkInterference())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
220 return true;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
221 }
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
222 return false;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
223 }