Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Hexagon/HexagonPseudo.td @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
comparison
equal deleted inserted replaced
133:c60214abe0e8 134:3a76565eade5
446 Requires<[HasV60T,UseHVX]>; 446 Requires<[HasV60T,UseHVX]>;
447 def PS_wselect: VSELInst<(outs HvxWR:$dst), 447 def PS_wselect: VSELInst<(outs HvxWR:$dst),
448 (ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>, 448 (ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>,
449 Requires<[HasV60T,UseHVX]>; 449 Requires<[HasV60T,UseHVX]>;
450 450
451 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
452 isCodeGenOnly = 1 in {
453 def PS_qtrue: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
454 V6_veqw.Itinerary, TypeCVI_VA>;
455 def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
456 V6_vgtw.Itinerary, TypeCVI_VA>;
457 }
458
451 // Store predicate. 459 // Store predicate.
452 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, 460 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
453 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in 461 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
454 def STriw_pred : STInst<(outs), 462 def STriw_pred : STInst<(outs),
455 (ins IntRegs:$addr, s32_0Imm:$off, PredRegs:$src1), 463 (ins IntRegs:$addr, s32_0Imm:$off, PredRegs:$src1),