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1 //===--- HexagonPseudo.td -------------------------------------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 // The pat frags in the definitions below need to have a named register,
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11 // otherwise i32 will be assumed regardless of the register class. The
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12 // name of the register does not matter.
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13 def I1 : PatLeaf<(i1 PredRegs:$R)>;
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14 def I32 : PatLeaf<(i32 IntRegs:$R)>;
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15 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
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16 def F32 : PatLeaf<(f32 IntRegs:$R)>;
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17 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
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18
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19 let PrintMethod = "printGlobalOperand" in {
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20 def globaladdress : Operand<i32>;
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21 def globaladdressExt : Operand<i32>;
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22 }
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23
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24 let isPseudo = 1 in {
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25 let isCodeGenOnly = 0 in
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26 def A2_iconst : Pseudo<(outs IntRegs:$Rd32),
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27 (ins s27_2Imm:$Ii), "${Rd32}=iconst(#${Ii})">;
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28
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29 def DUPLEX_Pseudo : InstHexagon<(outs),
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30 (ins s32_0Imm:$offset), "DUPLEX", [], "", DUPLEX, TypePSEUDO>;
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31 }
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32
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33 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
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34 isAsmParserOnly = 1 in
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35 def TFRI64_V2_ext : InstHexagon<(outs DoubleRegs:$dst),
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36 (ins s32_0Imm:$src1, s8_0Imm:$src2),
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37 "$dst=combine(#$src1,#$src2)", [], "",
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38 A2_combineii.Itinerary, TypeALU32_2op>, OpcodeHexagon;
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39
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40 // HI/LO Instructions
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41 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
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42 hasNewValue = 1, opNewValue = 0 in
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43 class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
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44 InstHexagon rootInst>
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45 : InstHexagon<(outs IntRegs:$dst),
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46 (ins u16_0Imm:$imm_value),
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47 "$dst"#RegHalf#"=#$imm_value", [], "",
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48 rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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49 bits<5> dst;
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50 bits<32> imm_value;
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51
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52 let Inst{27} = Rs;
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53 let Inst{26-24} = MajOp;
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54 let Inst{21} = MinOp;
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55 let Inst{20-16} = dst;
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56 let Inst{23-22} = imm_value{15-14};
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57 let Inst{13-0} = imm_value{13-0};
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58 }
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59
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60 let isAsmParserOnly = 1 in {
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61 def LO : REG_IMMED<".l", 0b0, 0b001, 0b1, A2_tfril>;
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62 def HI : REG_IMMED<".h", 0b0, 0b010, 0b1, A2_tfrih>;
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63 }
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64
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65 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in {
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66 def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
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67 "$Rd = CONST32(#$v)", []>;
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68 def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
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69 "$Rd = CONST64(#$v)", []>;
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70 }
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71
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72 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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73 isCodeGenOnly = 1 in
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74 def PS_true : InstHexagon<(outs PredRegs:$dst), (ins), "",
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75 [(set I1:$dst, 1)], "", C2_orn.Itinerary, TypeCR>;
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76
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77 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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78 isCodeGenOnly = 1 in
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79 def PS_false : InstHexagon<(outs PredRegs:$dst), (ins), "",
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80 [(set I1:$dst, 0)], "", C2_andn.Itinerary, TypeCR>;
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81
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82 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
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83 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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84 ".error \"should not emit\" ", []>;
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85
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86 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
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87 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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88 ".error \"should not emit\" ", []>;
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89
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90
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91 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
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92 Defs = [PC, LC0], Uses = [SA0, LC0] in {
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93 def ENDLOOP0 : Endloop<(outs), (ins b30_2Imm:$offset),
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94 ":endloop0",
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95 []>;
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96 }
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97
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98 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
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99 Defs = [PC, LC1], Uses = [SA1, LC1] in {
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100 def ENDLOOP1 : Endloop<(outs), (ins b30_2Imm:$offset),
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101 ":endloop1",
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102 []>;
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103 }
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104
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105 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
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106 opExtendable = 0, hasSideEffects = 0 in
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107 class LOOP_iBase<string mnemonic, InstHexagon rootInst>
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108 : InstHexagon <(outs), (ins b30_2Imm:$offset, u10_0Imm:$src2),
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109 #mnemonic#"($offset,#$src2)",
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110 [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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111 bits<9> offset;
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112 bits<10> src2;
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113
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114 let IClass = 0b0110;
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115
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116 let Inst{27-22} = 0b100100;
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117 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
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118 let Inst{20-16} = src2{9-5};
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119 let Inst{12-8} = offset{8-4};
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120 let Inst{7-5} = src2{4-2};
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121 let Inst{4-3} = offset{3-2};
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122 let Inst{1-0} = src2{1-0};
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123 }
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124
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125 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
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126 opExtendable = 0, hasSideEffects = 0 in
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127 class LOOP_rBase<string mnemonic, InstHexagon rootInst>
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128 : InstHexagon<(outs), (ins b30_2Imm:$offset, IntRegs:$src2),
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129 #mnemonic#"($offset,$src2)",
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130 [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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131 bits<9> offset;
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132 bits<5> src2;
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133
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134 let IClass = 0b0110;
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135
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136 let Inst{27-22} = 0b000000;
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137 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
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138 let Inst{20-16} = src2;
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139 let Inst{12-8} = offset{8-4};
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140 let Inst{4-3} = offset{3-2};
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141 }
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142
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143 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
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144 opExtendable = 0 in {
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145 def J2_loop0iext : LOOP_iBase<"loop0", J2_loop0i>;
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146 def J2_loop1iext : LOOP_iBase<"loop1", J2_loop1i>;
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147 }
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148
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149 // Interestingly only loop0's appear to set usr.lpcfg
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150 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
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151 def J2_loop0rext : LOOP_rBase<"loop0", J2_loop0r>;
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152 def J2_loop1rext : LOOP_rBase<"loop1", J2_loop1r>;
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153 }
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154
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155 let isCall = 1, hasSideEffects = 1, isPredicable = 0,
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156 isExtended = 0, isExtendable = 1, opExtendable = 0,
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157 isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
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158 class T_Call<string ExtStr>
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159 : InstHexagon<(outs), (ins a30_2Imm:$dst),
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160 "call " # ExtStr # "$dst", [], "", J2_call.Itinerary, TypeJ>,
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161 OpcodeHexagon {
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162 let BaseOpcode = "call";
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163 bits<24> dst;
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164
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165 let IClass = 0b0101;
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166 let Inst{27-25} = 0b101;
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167 let Inst{24-16,13-1} = dst{23-2};
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168 let Inst{0} = 0b0;
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169 }
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170
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171 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
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172 isPredicable = 0 in
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173 def CALLProfile : T_Call<"">;
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174
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175 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
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176 Defs = [PC, R31, R6, R7, P0] in
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177 def PS_call_stk : T_Call<"">;
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178
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179 // Call, no return.
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180 let isCall = 1, hasSideEffects = 1, cofMax1 = 1, isCodeGenOnly = 1 in
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181 def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
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182 "callr $Rs", [], "", J2_callr.Itinerary, TypeJ>, OpcodeHexagon {
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183 bits<5> Rs;
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184 bits<2> Pu;
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185 let isPredicatedFalse = 1;
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186
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187 let IClass = 0b0101;
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188 let Inst{27-21} = 0b0000101;
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189 let Inst{20-16} = Rs;
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190 }
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191
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192 let isCall = 1, hasSideEffects = 1,
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193 isExtended = 0, isExtendable = 1, opExtendable = 0, isCodeGenOnly = 1,
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194 BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
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195 class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops,
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196 InstrItinClass itin>
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197 : Pseudo<(outs), iops, "">, PredRel {
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198 bits<2> Pu;
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199 bits<17> dst;
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200 let opExtentBits = nbits;
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201 let isPredicable = 0; // !if(isPred, 0, 1);
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202 let isPredicated = 0; // isPred;
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203 let isPredicatedFalse = isFalse;
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204 }
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205
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206 def PS_call_nr : Call_nr<24, 0, 0, (ins s32_0Imm:$Ii), J2_call.Itinerary>;
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207 //def PS_call_nrt: Call_nr<17, 1, 0, (ins PredRegs:$Pu, s32_0Imm:$dst),
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208 // J2_callt.Itinerary>;
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209 //def PS_call_nrf: Call_nr<17, 1, 1, (ins PredRegs:$Pu, s32_0Imm:$dst),
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210 // J2_callf.Itinerary>;
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211
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212 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
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213 isPredicable = 1, hasSideEffects = 0, InputType = "reg",
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214 cofMax1 = 1 in
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215 class T_JMPr <InstHexagon rootInst>
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216 : InstHexagon<(outs), (ins IntRegs:$dst), "jumpr $dst", [],
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217 "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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218 bits<5> dst;
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219
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220 let IClass = 0b0101;
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221 let Inst{27-21} = 0b0010100;
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222 let Inst{20-16} = dst;
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223 }
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224
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225 // A return through builtin_eh_return.
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226 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
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227 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
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228 def EH_RETURN_JMPR : T_JMPr<J2_jumpr>;
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229
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230 // Indirect tail-call.
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231 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
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232 isTerminator = 1, isCodeGenOnly = 1 in
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233 def PS_tailcall_r : T_JMPr<J2_jumpr>;
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234
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235 //
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236 // Direct tail-calls.
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237 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
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238 isTerminator = 1, isCodeGenOnly = 1 in
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239 def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>;
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240
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241 let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
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242 def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
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243
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244 // Generate frameindex addresses. The main reason for the offset operand is
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245 // that every instruction that is allowed to have frame index as an operand
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246 // will then have that operand followed by an immediate operand (the offset).
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247 // This simplifies the frame-index elimination code.
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248 //
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249 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
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250 isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0, isExtendable = 1,
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251 isExtentSigned = 1, opExtentBits = 16, opExtentAlign = 0 in {
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252 let opExtendable = 2 in
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253 def PS_fi : Pseudo<(outs IntRegs:$Rd),
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254 (ins IntRegs:$fi, s32_0Imm:$off), "">;
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255 let opExtendable = 3 in
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256 def PS_fia : Pseudo<(outs IntRegs:$Rd),
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257 (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
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258 }
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259
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260 class CondStr<string CReg, bit True, bit New> {
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261 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
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262 }
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263 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
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264 string S = Mnemonic # !if(Taken, ":t", ":nt");
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265 }
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266 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
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267 hasSideEffects = 0, InputType = "reg", cofMax1 = 1 in
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268 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak, InstHexagon rootInst>
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269 : InstHexagon<(outs), (ins PredRegs:$src, IntRegs:$dst),
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270 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
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271 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst",
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272 [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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273
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274 let isTaken = isTak;
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275 let isPredicatedFalse = PredNot;
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276 let isPredicatedNew = isPredNew;
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277 bits<2> src;
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278 bits<5> dst;
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279
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280 let IClass = 0b0101;
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281
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282 let Inst{27-22} = 0b001101;
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283 let Inst{21} = PredNot;
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284 let Inst{20-16} = dst;
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285 let Inst{12} = isTak;
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286 let Inst{11} = isPredNew;
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287 let Inst{9-8} = src;
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288 }
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289
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290 let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1,
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291 isBarrier = 1, BaseOpcode = "JMPret" in {
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292 def PS_jmpret : T_JMPr<J2_jumpr>, PredNewRel;
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293 def PS_jmprett : T_JMPr_c<0, 0, 0, J2_jumprt>, PredNewRel;
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294 def PS_jmpretf : T_JMPr_c<1, 0, 0, J2_jumprf>, PredNewRel;
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295 def PS_jmprettnew : T_JMPr_c<0, 1, 0, J2_jumprtnew>, PredNewRel;
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296 def PS_jmpretfnew : T_JMPr_c<1, 1, 0, J2_jumprfnew>, PredNewRel;
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297 def PS_jmprettnewpt : T_JMPr_c<0, 1, 1, J2_jumprtnewpt>, PredNewRel;
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298 def PS_jmpretfnewpt : T_JMPr_c<1, 1, 1, J2_jumprfnewpt>, PredNewRel;
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299 }
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300
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301 //defm V6_vtran2x2_map : HexagonMapping<(outs HvxVR:$Vy32, HvxVR:$Vx32), (ins HvxVR:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, HvxVR:$Vx32in, IntRegs:$Rt32)>;
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302
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303 // The reason for the custom inserter is to record all ALLOCA instructions
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304 // in MachineFunctionInfo.
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305 let Defs = [R29], hasSideEffects = 1 in
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306 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
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307 (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
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308
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309 // Load predicate.
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310 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
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311 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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312 def LDriw_pred : LDInst<(outs PredRegs:$dst),
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313 (ins IntRegs:$addr, s32_0Imm:$off),
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314 ".error \"should not emit\"", []>;
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315
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316 // Load modifier.
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317 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
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318 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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319 def LDriw_mod : LDInst<(outs ModRegs:$dst),
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320 (ins IntRegs:$addr, s32_0Imm:$off),
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321 ".error \"should not emit\"", []>;
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322
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323
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324 let isCodeGenOnly = 1, isPseudo = 1 in
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325 def PS_pselect: InstHexagon<(outs DoubleRegs:$Rd),
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326 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
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327 ".error \"should not emit\" ", [], "", A2_tfrpt.Itinerary, TypeALU32_2op>;
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328
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329 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
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330 isPredicable = 1,
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331 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
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332 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
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333 class T_JMP: InstHexagon<(outs), (ins b30_2Imm:$dst),
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334 "jump $dst",
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335 [], "", J2_jump.Itinerary, TypeJ>, OpcodeHexagon {
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336 bits<24> dst;
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337 let IClass = 0b0101;
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338
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339 let Inst{27-25} = 0b100;
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340 let Inst{24-16} = dst{23-15};
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341 let Inst{13-1} = dst{14-2};
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342 }
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343
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344 // Restore registers and dealloc return function call.
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345 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
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346 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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347 def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP;
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348
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349 let isExtended = 1, opExtendable = 0 in
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350 def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP;
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351
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352 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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353 def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP;
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354
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355 let isExtended = 1, opExtendable = 0 in
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356 def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP;
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357 }
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358 }
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359
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360 // Restore registers and dealloc frame before a tail call.
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361 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
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362 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
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363
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364 let isExtended = 1, opExtendable = 0 in
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365 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<"">, PredRel;
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366
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367 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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368 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<"">, PredRel;
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369
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370 let isExtended = 1, opExtendable = 0 in
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371 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<"">, PredRel;
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372 }
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373 }
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374
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375 // Save registers function call.
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376 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
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377 def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
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378
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379 let isExtended = 1, opExtendable = 0 in
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380 def SAVE_REGISTERS_CALL_V4_EXT : T_Call<"">, PredRel;
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381
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382 let Defs = [P0] in
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383 def SAVE_REGISTERS_CALL_V4STK : T_Call<"">, PredRel;
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384
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385 let Defs = [P0], isExtended = 1, opExtendable = 0 in
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386 def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<"">, PredRel;
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387
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388 let Defs = [R14, R15, R28] in
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389 def SAVE_REGISTERS_CALL_V4_PIC : T_Call<"">, PredRel;
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390
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391 let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
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392 def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<"">, PredRel;
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393
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394 let Defs = [R14, R15, R28, P0] in
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395 def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<"">, PredRel;
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396
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397 let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
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398 def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<"">, PredRel;
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399 }
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400
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401 // Vector store pseudos
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402 let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
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403 mayStore = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in
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404 class STrivv_template<RegisterClass RC, InstHexagon rootInst>
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405 : InstHexagon<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src),
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406 "", [], "", rootInst.Itinerary, rootInst.Type>;
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407
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408 def PS_vstorerw_ai: STrivv_template<HvxWR, V6_vS32b_ai>,
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409 Requires<[HasV60T,UseHVX]>;
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410 def PS_vstorerw_nt_ai: STrivv_template<HvxWR, V6_vS32b_nt_ai>,
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411 Requires<[HasV60T,UseHVX]>;
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412 def PS_vstorerwu_ai: STrivv_template<HvxWR, V6_vS32Ub_ai>,
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413 Requires<[HasV60T,UseHVX]>;
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414
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415 let isPseudo = 1, isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0 in
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416 def PS_vstorerq_ai: Pseudo<(outs),
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417 (ins IntRegs:$Rs, s32_0Imm:$Off, HvxQR:$Qt), "", []>,
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418 Requires<[HasV60T,UseHVX]>;
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419
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420 // Vector load pseudos
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421 let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
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422 mayLoad = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in
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423 class LDrivv_template<RegisterClass RC, InstHexagon rootInst>
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424 : InstHexagon<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off),
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425 "", [], "", rootInst.Itinerary, rootInst.Type>;
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426
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427 def PS_vloadrw_ai: LDrivv_template<HvxWR, V6_vL32b_ai>,
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428 Requires<[HasV60T,UseHVX]>;
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429 def PS_vloadrw_nt_ai: LDrivv_template<HvxWR, V6_vL32b_nt_ai>,
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430 Requires<[HasV60T,UseHVX]>;
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431 def PS_vloadrwu_ai: LDrivv_template<HvxWR, V6_vL32Ub_ai>,
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432 Requires<[HasV60T,UseHVX]>;
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433
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434 let isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in
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435 def PS_vloadrq_ai: Pseudo<(outs HvxQR:$Qd),
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436 (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>,
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437 Requires<[HasV60T,UseHVX]>;
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438
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439
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440 let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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441 class VSELInst<dag outs, dag ins, InstHexagon rootInst>
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442 : InstHexagon<outs, ins, "", [], "", rootInst.Itinerary, rootInst.Type>;
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443
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444 def PS_vselect: VSELInst<(outs HvxVR:$dst),
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445 (ins PredRegs:$src1, HvxVR:$src2, HvxVR:$src3), V6_vcmov>,
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446 Requires<[HasV60T,UseHVX]>;
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447 def PS_wselect: VSELInst<(outs HvxWR:$dst),
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448 (ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>,
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449 Requires<[HasV60T,UseHVX]>;
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450
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134
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451 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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452 isCodeGenOnly = 1 in {
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453 def PS_qtrue: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
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454 V6_veqw.Itinerary, TypeCVI_VA>;
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455 def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
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456 V6_vgtw.Itinerary, TypeCVI_VA>;
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457 }
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458
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121
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459 // Store predicate.
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460 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
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461 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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462 def STriw_pred : STInst<(outs),
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463 (ins IntRegs:$addr, s32_0Imm:$off, PredRegs:$src1),
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464 ".error \"should not emit\"", []>;
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465 // Store modifier.
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466 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
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467 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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468 def STriw_mod : STInst<(outs),
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469 (ins IntRegs:$addr, s32_0Imm:$off, ModRegs:$src1),
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470 ".error \"should not emit\"", []>;
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471
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472 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
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|
473 isAsmParserOnly = 1 in
|
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|
474 def TFRI64_V4 : InstHexagon<(outs DoubleRegs:$dst),
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475 (ins u64_0Imm:$src1),
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|
476 "$dst = #$src1", [], "",
|
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477 A2_combineii.Itinerary, TypeALU32_2op>, OpcodeHexagon;
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478
|
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479 // Hexagon doesn't have a vector multiply with C semantics.
|
|
|
480 // Instead, generate a pseudo instruction that gets expaneded into two
|
|
|
481 // scalar MPYI instructions.
|
|
|
482 // This is expanded by ExpandPostRAPseudos.
|
|
|
483 let isPseudo = 1 in
|
|
|
484 def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
|
|
|
485 (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>;
|
|
|
486
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|
|
487 let isPseudo = 1 in
|
|
|
488 def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
|
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|
489 (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [],
|
|
|
490 "$Rd = $Rx">;
|
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491
|
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492 def DuplexIClass0: InstDuplex < 0 >;
|
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|
493 def DuplexIClass1: InstDuplex < 1 >;
|
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|
494 def DuplexIClass2: InstDuplex < 2 >;
|
|
|
495 let isExtendable = 1 in {
|
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|
496 def DuplexIClass3: InstDuplex < 3 >;
|
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497 def DuplexIClass4: InstDuplex < 4 >;
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498 def DuplexIClass5: InstDuplex < 5 >;
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499 def DuplexIClass6: InstDuplex < 6 >;
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500 def DuplexIClass7: InstDuplex < 7 >;
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|
501 }
|
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|
502 def DuplexIClass8: InstDuplex < 8 >;
|
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|
503 def DuplexIClass9: InstDuplex < 9 >;
|
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504 def DuplexIClassA: InstDuplex < 0xA >;
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505 def DuplexIClassB: InstDuplex < 0xB >;
|
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|
506 def DuplexIClassC: InstDuplex < 0xC >;
|
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|
507 def DuplexIClassD: InstDuplex < 0xD >;
|
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|
508 def DuplexIClassE: InstDuplex < 0xE >;
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|
509 def DuplexIClassF: InstDuplex < 0xF >;
|
