Mercurial > hg > CbC > CbC_llvm

comparison test/CodeGen/RISCV/mem.ll @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
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children c2174574ed3a
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133:c60214abe0e8 134:3a76565eade5
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s -check-prefix=RV32I
4
5 ; Check indexed and unindexed, sext, zext and anyext loads
6
7 define i32 @lb(i8 *%a) nounwind {
8 ; RV32I-LABEL: lb:
9 ; RV32I: # %bb.0:
10 ; RV32I-NEXT: lb a1, 0(a0)
11 ; RV32I-NEXT: lb a0, 1(a0)
12 ; RV32I-NEXT: ret
13 %1 = getelementptr i8, i8* %a, i32 1
14 %2 = load i8, i8* %1
15 %3 = sext i8 %2 to i32
16 ; the unused load will produce an anyext for selection
17 %4 = load volatile i8, i8* %a
18 ret i32 %3
19 }
20
21 define i32 @lh(i16 *%a) nounwind {
22 ; RV32I-LABEL: lh:
23 ; RV32I: # %bb.0:
24 ; RV32I-NEXT: lh a1, 0(a0)
25 ; RV32I-NEXT: lh a0, 4(a0)
26 ; RV32I-NEXT: ret
27 %1 = getelementptr i16, i16* %a, i32 2
28 %2 = load i16, i16* %1
29 %3 = sext i16 %2 to i32
30 ; the unused load will produce an anyext for selection
31 %4 = load volatile i16, i16* %a
32 ret i32 %3
33 }
34
35 define i32 @lw(i32 *%a) nounwind {
36 ; RV32I-LABEL: lw:
37 ; RV32I: # %bb.0:
38 ; RV32I-NEXT: lw a1, 0(a0)
39 ; RV32I-NEXT: lw a0, 12(a0)
40 ; RV32I-NEXT: ret
41 %1 = getelementptr i32, i32* %a, i32 3
42 %2 = load i32, i32* %1
43 %3 = load volatile i32, i32* %a
44 ret i32 %2
45 }
46
47 define i32 @lbu(i8 *%a) nounwind {
48 ; RV32I-LABEL: lbu:
49 ; RV32I: # %bb.0:
50 ; RV32I-NEXT: lbu a1, 0(a0)
51 ; RV32I-NEXT: lbu a0, 4(a0)
52 ; RV32I-NEXT: add a0, a0, a1
53 ; RV32I-NEXT: ret
54 %1 = getelementptr i8, i8* %a, i32 4
55 %2 = load i8, i8* %1
56 %3 = zext i8 %2 to i32
57 %4 = load volatile i8, i8* %a
58 %5 = zext i8 %4 to i32
59 %6 = add i32 %3, %5
60 ret i32 %6
61 }
62
63 define i32 @lhu(i16 *%a) nounwind {
64 ; RV32I-LABEL: lhu:
65 ; RV32I: # %bb.0:
66 ; RV32I-NEXT: lhu a1, 0(a0)
67 ; RV32I-NEXT: lhu a0, 10(a0)
68 ; RV32I-NEXT: add a0, a0, a1
69 ; RV32I-NEXT: ret
70 %1 = getelementptr i16, i16* %a, i32 5
71 %2 = load i16, i16* %1
72 %3 = zext i16 %2 to i32
73 %4 = load volatile i16, i16* %a
74 %5 = zext i16 %4 to i32
75 %6 = add i32 %3, %5
76 ret i32 %6
77 }
78
79 ; Check indexed and unindexed stores
80
81 define void @sb(i8 *%a, i8 %b) nounwind {
82 ; RV32I-LABEL: sb:
83 ; RV32I: # %bb.0:
84 ; RV32I-NEXT: sb a1, 6(a0)
85 ; RV32I-NEXT: sb a1, 0(a0)
86 ; RV32I-NEXT: ret
87 store i8 %b, i8* %a
88 %1 = getelementptr i8, i8* %a, i32 6
89 store i8 %b, i8* %1
90 ret void
91 }
92
93 define void @sh(i16 *%a, i16 %b) nounwind {
94 ; RV32I-LABEL: sh:
95 ; RV32I: # %bb.0:
96 ; RV32I-NEXT: sh a1, 14(a0)
97 ; RV32I-NEXT: sh a1, 0(a0)
98 ; RV32I-NEXT: ret
99 store i16 %b, i16* %a
100 %1 = getelementptr i16, i16* %a, i32 7
101 store i16 %b, i16* %1
102 ret void
103 }
104
105 define void @sw(i32 *%a, i32 %b) nounwind {
106 ; RV32I-LABEL: sw:
107 ; RV32I: # %bb.0:
108 ; RV32I-NEXT: sw a1, 32(a0)
109 ; RV32I-NEXT: sw a1, 0(a0)
110 ; RV32I-NEXT: ret
111 store i32 %b, i32* %a
112 %1 = getelementptr i32, i32* %a, i32 8
113 store i32 %b, i32* %1
114 ret void
115 }
116
117 ; Check load and store to an i1 location
118 define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
119 ; RV32I-LABEL: load_sext_zext_anyext_i1:
120 ; RV32I: # %bb.0:
121 ; RV32I-NEXT: lb a1, 0(a0)
122 ; RV32I-NEXT: lbu a1, 1(a0)
123 ; RV32I-NEXT: lbu a0, 2(a0)
124 ; RV32I-NEXT: sub a0, a0, a1
125 ; RV32I-NEXT: ret
126 ; sextload i1
127 %1 = getelementptr i1, i1* %a, i32 1
128 %2 = load i1, i1* %1
129 %3 = sext i1 %2 to i32
130 ; zextload i1
131 %4 = getelementptr i1, i1* %a, i32 2
132 %5 = load i1, i1* %4
133 %6 = zext i1 %5 to i32
134 %7 = add i32 %3, %6
135 ; extload i1 (anyext). Produced as the load is unused.
136 %8 = load volatile i1, i1* %a
137 ret i32 %7
138 }
139
140 define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
141 ; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
142 ; RV32I: # %bb.0:
143 ; RV32I-NEXT: lb a1, 0(a0)
144 ; RV32I-NEXT: lbu a1, 1(a0)
145 ; RV32I-NEXT: lbu a0, 2(a0)
146 ; RV32I-NEXT: sub a0, a0, a1
147 ; RV32I-NEXT: ret
148 ; sextload i1
149 %1 = getelementptr i1, i1* %a, i32 1
150 %2 = load i1, i1* %1
151 %3 = sext i1 %2 to i16
152 ; zextload i1
153 %4 = getelementptr i1, i1* %a, i32 2
154 %5 = load i1, i1* %4
155 %6 = zext i1 %5 to i16
156 %7 = add i16 %3, %6
157 ; extload i1 (anyext). Produced as the load is unused.
158 %8 = load volatile i1, i1* %a
159 ret i16 %7
160 }
161
162 ; Check load and store to a global
163 @G = global i32 0
164
165 define i32 @lw_sw_global(i32 %a) nounwind {
166 ; TODO: the addi should be folded in to the lw/sw operations
167 ; RV32I-LABEL: lw_sw_global:
168 ; RV32I: # %bb.0:
169 ; RV32I-NEXT: lui a1, %hi(G)
170 ; RV32I-NEXT: addi a2, a1, %lo(G)
171 ; RV32I-NEXT: lw a1, 0(a2)
172 ; RV32I-NEXT: sw a0, 0(a2)
173 ; RV32I-NEXT: lui a2, %hi(G+36)
174 ; RV32I-NEXT: addi a2, a2, %lo(G+36)
175 ; RV32I-NEXT: lw a3, 0(a2)
176 ; RV32I-NEXT: sw a0, 0(a2)
177 ; RV32I-NEXT: mv a0, a1
178 ; RV32I-NEXT: ret
179 %1 = load volatile i32, i32* @G
180 store i32 %a, i32* @G
181 %2 = getelementptr i32, i32* @G, i32 9
182 %3 = load volatile i32, i32* %2
183 store i32 %a, i32* %2
184 ret i32 %1
185 }
186
187 ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
188 define i32 @lw_sw_constant(i32 %a) nounwind {
189 ; TODO: the addi should be folded in to the lw/sw
190 ; RV32I-LABEL: lw_sw_constant:
191 ; RV32I: # %bb.0:
192 ; RV32I-NEXT: lui a1, 912092
193 ; RV32I-NEXT: addi a2, a1, -273
194 ; RV32I-NEXT: lw a1, 0(a2)
195 ; RV32I-NEXT: sw a0, 0(a2)
196 ; RV32I-NEXT: mv a0, a1
197 ; RV32I-NEXT: ret
198 %1 = inttoptr i32 3735928559 to i32*
199 %2 = load volatile i32, i32* %1
200 store i32 %a, i32* %1
201 ret i32 %2
202 }