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comparison lib/Target/Mips/Mips64InstrInfo.td @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents e4204d083e25
children 60c9769439b8
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
18 // Unsigned Operand 18 // Unsigned Operand
19 def uimm16_64 : Operand<i64> { 19 def uimm16_64 : Operand<i64> {
20 let PrintMethod = "printUnsignedImm"; 20 let PrintMethod = "printUnsignedImm";
21 } 21 }
22 22
23 // Signed Operand
24 def simm10_64 : Operand<i64>;
25
26 def imm64: Operand<i64>;
27
23 // Transformation Function - get Imm - 32. 28 // Transformation Function - get Imm - 32.
24 def Subtract32 : SDNodeXForm<imm, [{ 29 def Subtract32 : SDNodeXForm<imm, [{
25 return getImm(N, (unsigned)N->getZExtValue() - 32); 30 return getImm(N, (unsigned)N->getZExtValue() - 32);
26 }]>; 31 }]>;
27 32
28 // shamt must fit in 6 bits. 33 // shamt must fit in 6 bits.
29 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 34 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
35
36 // Node immediate fits as 10-bit sign extended on target immediate.
37 // e.g. seqi, snei
38 def immSExt10_64 : PatLeaf<(i64 imm),
39 [{ return isInt<10>(N->getSExtValue()); }]>;
40
41 def immZExt16_64 : PatLeaf<(i64 imm),
42 [{ return isInt<16>(N->getZExtValue()); }]>;
30 43
31 //===----------------------------------------------------------------------===// 44 //===----------------------------------------------------------------------===//
32 // Instructions specific format 45 // Instructions specific format
33 //===----------------------------------------------------------------------===// 46 //===----------------------------------------------------------------------===//
34 let usesCustomInserter = 1 in { 47 let usesCustomInserter = 1 in {
51 //===----------------------------------------------------------------------===// 64 //===----------------------------------------------------------------------===//
52 // Instruction definition 65 // Instruction definition
53 //===----------------------------------------------------------------------===// 66 //===----------------------------------------------------------------------===//
54 let DecoderNamespace = "Mips64" in { 67 let DecoderNamespace = "Mips64" in {
55 /// Arithmetic Instructions (ALU Immediate) 68 /// Arithmetic Instructions (ALU Immediate)
56 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>; 69 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
57 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, IIArith, 70 ISA_MIPS3_NOT_32R6_64R6;
71 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
58 immSExt16, add>, 72 immSExt16, add>,
59 ADDI_FM<0x19>, IsAsCheapAsAMove; 73 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
60 74
61 let isCodeGenOnly = 1 in { 75 let isCodeGenOnly = 1 in {
62 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 76 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
63 SLTI_FM<0xa>; 77 SLTI_FM<0xa>;
64 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 78 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
65 SLTI_FM<0xb>; 79 SLTI_FM<0xb>;
66 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, IILogic, immZExt16, 80 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
67 and>,
68 ADDI_FM<0xc>; 81 ADDI_FM<0xc>;
69 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, IILogic, immZExt16, 82 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
70 or>,
71 ADDI_FM<0xd>; 83 ADDI_FM<0xd>;
72 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, IILogic, immZExt16, 84 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
73 xor>,
74 ADDI_FM<0xe>; 85 ADDI_FM<0xe>;
75 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM; 86 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
76 } 87 }
77 88
78 /// Arithmetic Instructions (3-Operand, R-Type) 89 /// Arithmetic Instructions (3-Operand, R-Type)
79 def DADD : ArithLogicR<"dadd", GPR64Opnd>, ADD_FM<0, 0x2c>; 90 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
80 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, IIArith, add>, 91 ISA_MIPS3;
81 ADD_FM<0, 0x2d>; 92 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
82 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, IIArith, sub>, 93 ISA_MIPS3;
83 ADD_FM<0, 0x2f>; 94 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
95 ISA_MIPS3;
96 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
97 ISA_MIPS3;
84 98
85 let isCodeGenOnly = 1 in { 99 let isCodeGenOnly = 1 in {
86 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; 100 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
87 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>; 101 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
88 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, IIArith, and>, ADD_FM<0, 0x24>; 102 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
89 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, IIArith, or>, ADD_FM<0, 0x25>; 103 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
90 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, IIArith, xor>, ADD_FM<0, 0x26>; 104 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
91 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>; 105 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
92 } 106 }
93 107
94 /// Shift Instructions 108 /// Shift Instructions
95 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, shl, immZExt6>, 109 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
96 SRA_FM<0x38, 0>; 110 SRA_FM<0x38, 0>, ISA_MIPS3;
97 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, srl, immZExt6>, 111 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
98 SRA_FM<0x3a, 0>; 112 SRA_FM<0x3a, 0>, ISA_MIPS3;
99 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, sra, immZExt6>, 113 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
100 SRA_FM<0x3b, 0>; 114 SRA_FM<0x3b, 0>, ISA_MIPS3;
101 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, shl>, SRLV_FM<0x14, 0>; 115 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
102 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, srl>, SRLV_FM<0x16, 0>; 116 SRLV_FM<0x14, 0>, ISA_MIPS3;
103 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, sra>, SRLV_FM<0x17, 0>; 117 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
104 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd>, SRA_FM<0x3c, 0>; 118 SRLV_FM<0x16, 0>, ISA_MIPS3;
105 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 0>; 119 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
106 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd>, SRA_FM<0x3f, 0>; 120 SRLV_FM<0x17, 0>, ISA_MIPS3;
121 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
122 SRA_FM<0x3c, 0>, ISA_MIPS3;
123 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
124 SRA_FM<0x3e, 0>, ISA_MIPS3;
125 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
126 SRA_FM<0x3f, 0>, ISA_MIPS3;
107 127
108 // Rotate Instructions 128 // Rotate Instructions
109 let Predicates = [HasMips64r2, HasStdEnc] in { 129 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
110 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, rotr, immZExt6>, 130 immZExt6>,
111 SRA_FM<0x3a, 1>; 131 SRA_FM<0x3a, 1>, ISA_MIPS64R2;
112 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, rotr>, 132 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
113 SRLV_FM<0x16, 1>; 133 SRLV_FM<0x16, 1>, ISA_MIPS64R2;
114 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 1>; 134 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
115 } 135 SRA_FM<0x3e, 1>, ISA_MIPS64R2;
116 136
117 /// Load and Store Instructions 137 /// Load and Store Instructions
118 /// aligned 138 /// aligned
119 let isCodeGenOnly = 1 in { 139 let isCodeGenOnly = 1 in {
120 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, IILoad>, LW_FM<0x20>; 140 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
121 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, IILoad>, LW_FM<0x24>; 141 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
122 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, IILoad>, LW_FM<0x21>; 142 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
123 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, IILoad>, LW_FM<0x25>; 143 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
124 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, IILoad>, LW_FM<0x23>; 144 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
125 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, IIStore>, LW_FM<0x28>; 145 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
126 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, IIStore>, LW_FM<0x29>; 146 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
127 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, IIStore>, LW_FM<0x2b>; 147 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
128 } 148 }
129 149
130 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, IILoad>, LW_FM<0x27>; 150 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
131 def LD : Load<"ld", GPR64Opnd, load, IILoad>, LW_FM<0x37>; 151 def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
132 def SD : Store<"sd", GPR64Opnd, store, IIStore>, LW_FM<0x3f>; 152 def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
133 153
134 /// load/store left/right 154 /// load/store left/right
135 let isCodeGenOnly = 1 in { 155 let isCodeGenOnly = 1 in {
136 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, IILoad>, LW_FM<0x22>; 156 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
137 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, IILoad>, LW_FM<0x26>; 157 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
138 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, IIStore>, LW_FM<0x2a>; 158 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
139 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, IIStore>, LW_FM<0x2e>; 159 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
140 } 160 }
141 161
142 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, IILoad>, LW_FM<0x1a>; 162 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
143 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, IILoad>, LW_FM<0x1b>; 163 ISA_MIPS3_NOT_32R6_64R6;
144 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, IIStore>, LW_FM<0x2c>; 164 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
145 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, IIStore>, LW_FM<0x2d>; 165 ISA_MIPS3_NOT_32R6_64R6;
166 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
167 ISA_MIPS3_NOT_32R6_64R6;
168 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
169 ISA_MIPS3_NOT_32R6_64R6;
146 170
147 /// Load-linked, Store-conditional 171 /// Load-linked, Store-conditional
148 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>; 172 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
149 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>; 173 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
150 174
151 /// Jump and Branch Instructions 175 /// Jump and Branch Instructions
152 let isCodeGenOnly = 1 in { 176 let isCodeGenOnly = 1 in {
153 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>; 177 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
154 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>; 178 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
155 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>; 179 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
156 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>; 180 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
157 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; 181 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
158 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; 182 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
159 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; 183 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
160 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; 184 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
161 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; 185 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
162 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>; 186 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
163 } 187 }
188
189 def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
190 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
164 191
165 /// Multiply and Divide Instructions. 192 /// Multiply and Divide Instructions.
166 def DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI0_64, LO0_64]>, 193 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
167 MULT_FM<0, 0x1c>; 194 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
168 def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI0_64, LO0_64]>, 195 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
169 MULT_FM<0, 0x1d>; 196 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
170 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 197 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
171 IIImult>; 198 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
172 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 199 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
173 IIImult>; 200 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
174 def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1e>; 201 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
175 def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1f>; 202 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
203 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
204 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
176 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 205 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
177 IIIdiv, 0, 1, 1>; 206 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
178 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 207 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
179 IIIdiv, 0, 1, 1>; 208 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
180 209
181 let isCodeGenOnly = 1 in { 210 let isCodeGenOnly = 1 in {
182 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>; 211 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
183 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>; 212 ISA_MIPS3_NOT_32R6_64R6;
184 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>; 213 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
185 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>; 214 ISA_MIPS3_NOT_32R6_64R6;
186 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>; 215 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
187 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>; 216 ISA_MIPS3_NOT_32R6_64R6;
188 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>; 217 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
218 ISA_MIPS3_NOT_32R6_64R6;
219 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
220 ISA_MIPS3_NOT_32R6_64R6;
221 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
222 ISA_MIPS3_NOT_32R6_64R6;
223 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
189 224
190 /// Sign Ext In Register Instructions. 225 /// Sign Ext In Register Instructions.
191 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>; 226 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
192 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd>, SEB_FM<0x18, 0x20>; 227 ISA_MIPS32R2;
228 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
229 ISA_MIPS32R2;
193 } 230 }
194 231
195 /// Count Leading 232 /// Count Leading
196 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>; 233 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
197 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>; 234 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
198 235
199 /// Double Word Swap Bytes/HalfWords 236 /// Double Word Swap Bytes/HalfWords
200 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>; 237 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
201 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>; 238 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
202 239
203 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; 240 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
204 241
205 let isCodeGenOnly = 1 in 242 let isCodeGenOnly = 1 in
206 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; 243 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
213 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>; 250 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
214 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>; 251 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
215 252
216 let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 253 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
217 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 254 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
218 "dsll\t$rd, $rt, 32", [], IIArith>; 255 "dsll\t$rd, $rt, 32", [], II_DSLL>;
219 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 256 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
220 "sll\t$rd, $rt, 0", [], IIArith>; 257 "sll\t$rd, $rt, 0", [], II_SLL>;
221 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 258 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
222 "sll\t$rd, $rt, 0", [], IIArith>; 259 "sll\t$rd, $rt, 0", [], II_SLL>;
223 } 260 }
224 } 261
262 // We need the following pseudo instruction to avoid offset calculation for
263 // long branches. See the comment in file MipsLongBranch.cpp for detailed
264 // explanation.
265
266 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
267 // where %PART may be %hi or %lo, depending on the relocation kind
268 // that $tgt is annotated with.
269 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
270 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
271
272 // Cavium Octeon cmMIPS instructions
273 let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
274 AdditionalPredicates = [HasCnMips] in {
275
276 class Count1s<string opstr, RegisterOperand RO>:
277 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
278 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
279 let TwoOperandAliasConstraint = "$rd = $rs";
280 }
281
282 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
283 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
284 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
285 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
286 NoItinerary, FrmR, opstr> {
287 let TwoOperandAliasConstraint = "$rt = $rs";
288 }
289
290 class SetCC64_R<string opstr, PatFrag cond_op> :
291 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
292 !strconcat(opstr, "\t$rd, $rs, $rt"),
293 [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
294 II_SEQ_SNE, FrmR, opstr> {
295 let TwoOperandAliasConstraint = "$rd = $rs";
296 }
297
298 class SetCC64_I<string opstr, PatFrag cond_op>:
299 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
300 !strconcat(opstr, "\t$rt, $rs, $imm10"),
301 [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
302 II_SEQI_SNEI, FrmI, opstr> {
303 let TwoOperandAliasConstraint = "$rt = $rs";
304 }
305
306 // Unsigned Byte Add
307 let Pattern = [(set GPR64Opnd:$rd,
308 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
309 def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
310 ADD_FM<0x1c, 0x28>;
311
312 // Multiply Doubleword to GPR
313 let Defs = [HI0, LO0, P0, P1, P2] in
314 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
315 ADD_FM<0x1c, 0x03>;
316
317 // Extract a signed bit field /+32
318 def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
319 def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
320
321 // Clear and insert a bit field /+32
322 def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
323 def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
324
325 // Move to multiplier/product register
326 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
327 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
328 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
329 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
330 def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
331 def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
332
333 // Count Ones in a Word/Doubleword
334 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
335 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
336
337 // Set on equal/not equal
338 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
339 def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
340 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
341 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
342
343 // 192-bit x 64-bit Unsigned Multiply and Add
344 let Defs = [P0, P1, P2] in
345 def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
346 ADD_FM<0x1c, 0x11>;
347
348 // 64-bit Unsigned Multiply and Add Move
349 let Defs = [MPL0, P0, P1, P2] in
350 def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
351 ADD_FM<0x1c, 0x10>;
352
353 // 64-bit Unsigned Multiply and Add
354 let Defs = [MPL1, MPL2, P0, P1, P2] in
355 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
356 ADD_FM<0x1c, 0x0f>;
357
358 }
359
360 }
361
225 //===----------------------------------------------------------------------===// 362 //===----------------------------------------------------------------------===//
226 // Arbitrary patterns that map to one or more instructions 363 // Arbitrary patterns that map to one or more instructions
227 //===----------------------------------------------------------------------===// 364 //===----------------------------------------------------------------------===//
228 365
229 // extended loads 366 // extended loads
230 let Predicates = [HasStdEnc] in { 367 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
231 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 368 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
232 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 369 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
233 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 370 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
234 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
235 }
236 371
237 // hi/lo relocs 372 // hi/lo relocs
238 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 373 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
239 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 374 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
240 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 375 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
283 defm : SetgePats<GPR64, SLT64, SLTu64>; 418 defm : SetgePats<GPR64, SLT64, SLTu64>;
284 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; 419 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
285 420
286 // truncate 421 // truncate
287 def : MipsPat<(i32 (trunc GPR64:$src)), 422 def : MipsPat<(i32 (trunc GPR64:$src)),
288 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>, 423 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
289 Requires<[HasStdEnc]>;
290 424
291 // 32-to-64-bit extension 425 // 32-to-64-bit extension
292 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; 426 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
293 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; 427 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
294 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; 428 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
301 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; 435 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
302 436
303 //===----------------------------------------------------------------------===// 437 //===----------------------------------------------------------------------===//
304 // Instruction aliases 438 // Instruction aliases
305 //===----------------------------------------------------------------------===// 439 //===----------------------------------------------------------------------===//
306 def : InstAlias<"move $dst, $src", 440 def : MipsInstAlias<"move $dst, $src",
307 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 441 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
308 Requires<[HasMips64]>; 442 GPR_64;
309 def : InstAlias<"daddu $rs, $rt, $imm", 443 def : MipsInstAlias<"daddu $rs, $rt, $imm",
310 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 444 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
311 0>; 445 0>;
312 def : InstAlias<"dadd $rs, $rt, $imm", 446 def : MipsInstAlias<"dadd $rs, $rt, $imm",
313 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 447 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
314 0>; 448 0>, ISA_MIPS3_NOT_32R6_64R6;
449 def : MipsInstAlias<"daddu $rs, $imm",
450 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
451 0>;
452 def : MipsInstAlias<"dadd $rs, $imm",
453 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
454 0>, ISA_MIPS3_NOT_32R6_64R6;
455 def : MipsInstAlias<"add $rs, $imm",
456 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
457 0>;
458 def : MipsInstAlias<"addu $rs, $imm",
459 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
460 0>;
461 def : MipsInstAlias<"dsll $rd, $rt, $rs",
462 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
463 ISA_MIPS3;
464 def : MipsInstAlias<"dsubu $rt, $rs, $imm",
465 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
466 InvertedImOperand64:$imm), 0>;
467 def : MipsInstAlias<"dsubi $rs, $rt, $imm",
468 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
469 InvertedImOperand64:$imm),
470 0>, ISA_MIPS3_NOT_32R6_64R6;
471 def : MipsInstAlias<"dsubi $rs, $imm",
472 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
473 InvertedImOperand64:$imm),
474 0>, ISA_MIPS3_NOT_32R6_64R6;
475 def : MipsInstAlias<"dsub $rs, $rt, $imm",
476 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
477 InvertedImOperand64:$imm),
478 0>, ISA_MIPS3_NOT_32R6_64R6;
479 def : MipsInstAlias<"dsub $rs, $imm",
480 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
481 InvertedImOperand64:$imm),
482 0>, ISA_MIPS3_NOT_32R6_64R6;
483 def : MipsInstAlias<"dsubu $rs, $imm",
484 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
485 InvertedImOperand64:$imm),
486 0>;
487 def : MipsInstAlias<"dsra $rd, $rt, $rs",
488 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
489 ISA_MIPS3;
490 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
491 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
492 ISA_MIPS3;
493
494 class LoadImm64< string instr_asm, Operand Od, RegisterOperand RO> :
495 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
496 !strconcat(instr_asm, "\t$rt, $imm64")> ;
497 def LoadImm64Reg : LoadImm64<"dli", imm64, GPR64Opnd>;
315 498
316 /// Move between CPU and coprocessor registers 499 /// Move between CPU and coprocessor registers
317 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in { 500 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
318 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>; 501 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
319 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>; 502 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
320 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>; 503 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
321 def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>; 504 def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
322 } 505 }
323 506
324 // Two operand (implicit 0 selector) versions: 507 // Two operand (implicit 0 selector) versions:
325 def : InstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 508 def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
326 def : InstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 509 def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
327 def : InstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 510 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
328 def : InstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 511 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
329 512