0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
3 // The LLVM Compiler Infrastructure
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
4 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
5 // This file is distributed under the University of Illinois Open Source
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
6 // License. See LICENSE.TXT for details.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
7 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
8 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
9 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
10 // This file describes Mips64 instructions.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
11 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
12 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
13
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
14 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
15 // Mips Operand, Complex Patterns and Transformations Definitions.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
16 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
17
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
18 // Unsigned Operand
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
19 def uimm16_64 : Operand<i64> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
20 let PrintMethod = "printUnsignedImm";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
21 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
22
|
|
77
|
23 // Signed Operand
|
|
|
24 def simm10_64 : Operand<i64>;
|
|
|
25
|
|
|
26 def imm64: Operand<i64>;
|
|
|
27
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
28 // Transformation Function - get Imm - 32.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
29 def Subtract32 : SDNodeXForm<imm, [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
30 return getImm(N, (unsigned)N->getZExtValue() - 32);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
31 }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
32
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
33 // shamt must fit in 6 bits.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
34 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
35
|
|
77
|
36 // Node immediate fits as 10-bit sign extended on target immediate.
|
|
|
37 // e.g. seqi, snei
|
|
|
38 def immSExt10_64 : PatLeaf<(i64 imm),
|
|
|
39 [{ return isInt<10>(N->getSExtValue()); }]>;
|
|
|
40
|
|
|
41 def immZExt16_64 : PatLeaf<(i64 imm),
|
|
|
42 [{ return isInt<16>(N->getZExtValue()); }]>;
|
|
|
43
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
44 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
45 // Instructions specific format
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
46 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
47 let usesCustomInserter = 1 in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
48 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
49 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
50 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
51 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
52 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
53 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
54 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
55 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
56 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
57
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
58 /// Pseudo instructions for loading and storing accumulator registers.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
59 let isPseudo = 1, isCodeGenOnly = 1 in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
60 def LOAD_ACC128 : Load<"", ACC128>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
61 def STORE_ACC128 : Store<"", ACC128>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
62 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
63
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
64 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
65 // Instruction definition
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
66 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
67 let DecoderNamespace = "Mips64" in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
68 /// Arithmetic Instructions (ALU Immediate)
|
|
77
|
69 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
|
|
|
70 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
71 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
72 immSExt16, add>,
|
|
77
|
73 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
74
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
75 let isCodeGenOnly = 1 in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
76 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
77 SLTI_FM<0xa>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
78 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
79 SLTI_FM<0xb>;
|
|
77
|
80 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
81 ADDI_FM<0xc>;
|
|
77
|
82 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
83 ADDI_FM<0xd>;
|
|
77
|
84 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
85 ADDI_FM<0xe>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
86 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
87 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
88
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
89 /// Arithmetic Instructions (3-Operand, R-Type)
|
|
77
|
90 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
|
|
|
91 ISA_MIPS3;
|
|
|
92 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
|
|
|
93 ISA_MIPS3;
|
|
|
94 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
|
|
|
95 ISA_MIPS3;
|
|
|
96 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
|
|
|
97 ISA_MIPS3;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
98
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
99 let isCodeGenOnly = 1 in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
100 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
101 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
|
|
77
|
102 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
|
|
|
103 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
|
|
|
104 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
105 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
106 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
107
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
108 /// Shift Instructions
|
|
77
|
109 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
|
|
|
110 SRA_FM<0x38, 0>, ISA_MIPS3;
|
|
|
111 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
|
|
|
112 SRA_FM<0x3a, 0>, ISA_MIPS3;
|
|
|
113 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
|
|
|
114 SRA_FM<0x3b, 0>, ISA_MIPS3;
|
|
|
115 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
|
|
|
116 SRLV_FM<0x14, 0>, ISA_MIPS3;
|
|
|
117 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
|
|
|
118 SRLV_FM<0x16, 0>, ISA_MIPS3;
|
|
|
119 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
|
|
|
120 SRLV_FM<0x17, 0>, ISA_MIPS3;
|
|
|
121 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
|
|
|
122 SRA_FM<0x3c, 0>, ISA_MIPS3;
|
|
|
123 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
|
|
|
124 SRA_FM<0x3e, 0>, ISA_MIPS3;
|
|
|
125 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
|
|
|
126 SRA_FM<0x3f, 0>, ISA_MIPS3;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
127
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
128 // Rotate Instructions
|
|
77
|
129 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
|
|
|
130 immZExt6>,
|
|
|
131 SRA_FM<0x3a, 1>, ISA_MIPS64R2;
|
|
|
132 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
|
|
|
133 SRLV_FM<0x16, 1>, ISA_MIPS64R2;
|
|
|
134 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
|
|
|
135 SRA_FM<0x3e, 1>, ISA_MIPS64R2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
136
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
137 /// Load and Store Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
138 /// aligned
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
139 let isCodeGenOnly = 1 in {
|
|
77
|
140 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
|
|
|
141 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
|
|
|
142 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
|
|
|
143 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
|
|
|
144 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
|
|
|
145 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
|
|
|
146 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
|
|
|
147 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
148 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
149
|
|
77
|
150 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
|
|
|
151 def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
|
|
|
152 def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
153
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
154 /// load/store left/right
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
155 let isCodeGenOnly = 1 in {
|
|
77
|
156 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
|
|
|
157 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
|
|
|
158 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
|
|
|
159 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
160 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
161
|
|
77
|
162 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
|
|
|
163 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
164 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
|
|
|
165 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
166 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
|
|
|
167 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
168 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
|
|
|
169 ISA_MIPS3_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
170
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
171 /// Load-linked, Store-conditional
|
|
77
|
172 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
173 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
174
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
175 /// Jump and Branch Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
176 let isCodeGenOnly = 1 in {
|
|
77
|
177 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
|
|
|
178 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
|
|
|
179 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
|
|
|
180 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
|
|
|
181 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
|
|
|
182 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
|
|
|
183 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
|
|
|
184 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
|
|
|
185 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
|
|
|
186 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
187 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
188
|
|
77
|
189 def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
|
|
|
190 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
|
|
|
191
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
192 /// Multiply and Divide Instructions.
|
|
77
|
193 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
|
194 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
195 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
|
196 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
197 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
|
|
77
|
198 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
199 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
|
|
77
|
200 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
201 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
|
202 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
203 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
|
204 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
205 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
|
|
77
|
206 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
207 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
|
|
77
|
208 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
209
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
210 let isCodeGenOnly = 1 in {
|
|
77
|
211 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
|
|
|
212 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
213 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
|
|
|
214 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
215 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
|
|
|
216 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
217 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
|
|
|
218 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
219 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
|
|
|
220 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
221 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
|
|
|
222 ISA_MIPS3_NOT_32R6_64R6;
|
|
|
223 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
224
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
225 /// Sign Ext In Register Instructions.
|
|
77
|
226 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
|
|
|
227 ISA_MIPS32R2;
|
|
|
228 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
|
|
|
229 ISA_MIPS32R2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
230 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
231
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
232 /// Count Leading
|
|
77
|
233 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
|
|
|
234 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
235
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
236 /// Double Word Swap Bytes/HalfWords
|
|
77
|
237 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
|
|
|
238 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
239
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
240 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
241
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
242 let isCodeGenOnly = 1 in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
243 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
244
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
245 def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
246 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
247 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
248
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
249 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
250 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
251 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
252
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
253 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
254 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
|
|
77
|
255 "dsll\t$rd, $rt, 32", [], II_DSLL>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
256 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
|
|
77
|
257 "sll\t$rd, $rt, 0", [], II_SLL>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
258 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
|
|
77
|
259 "sll\t$rd, $rt, 0", [], II_SLL>;
|
|
|
260 }
|
|
|
261
|
|
|
262 // We need the following pseudo instruction to avoid offset calculation for
|
|
|
263 // long branches. See the comment in file MipsLongBranch.cpp for detailed
|
|
|
264 // explanation.
|
|
|
265
|
|
|
266 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
|
|
|
267 // where %PART may be %hi or %lo, depending on the relocation kind
|
|
|
268 // that $tgt is annotated with.
|
|
|
269 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
|
|
|
270 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
|
|
|
271
|
|
|
272 // Cavium Octeon cmMIPS instructions
|
|
|
273 let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
|
|
|
274 AdditionalPredicates = [HasCnMips] in {
|
|
|
275
|
|
|
276 class Count1s<string opstr, RegisterOperand RO>:
|
|
|
277 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
|
|
278 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
|
|
|
279 let TwoOperandAliasConstraint = "$rd = $rs";
|
|
|
280 }
|
|
|
281
|
|
|
282 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
|
|
|
283 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
|
|
|
284 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
|
|
|
285 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
|
|
|
286 NoItinerary, FrmR, opstr> {
|
|
|
287 let TwoOperandAliasConstraint = "$rt = $rs";
|
|
|
288 }
|
|
|
289
|
|
|
290 class SetCC64_R<string opstr, PatFrag cond_op> :
|
|
|
291 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
|
|
|
292 !strconcat(opstr, "\t$rd, $rs, $rt"),
|
|
|
293 [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
|
|
|
294 II_SEQ_SNE, FrmR, opstr> {
|
|
|
295 let TwoOperandAliasConstraint = "$rd = $rs";
|
|
|
296 }
|
|
|
297
|
|
|
298 class SetCC64_I<string opstr, PatFrag cond_op>:
|
|
|
299 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
|
|
|
300 !strconcat(opstr, "\t$rt, $rs, $imm10"),
|
|
|
301 [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
|
|
|
302 II_SEQI_SNEI, FrmI, opstr> {
|
|
|
303 let TwoOperandAliasConstraint = "$rt = $rs";
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
304 }
|
|
77
|
305
|
|
|
306 // Unsigned Byte Add
|
|
|
307 let Pattern = [(set GPR64Opnd:$rd,
|
|
|
308 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
|
|
|
309 def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
|
|
|
310 ADD_FM<0x1c, 0x28>;
|
|
|
311
|
|
|
312 // Multiply Doubleword to GPR
|
|
|
313 let Defs = [HI0, LO0, P0, P1, P2] in
|
|
|
314 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
|
|
|
315 ADD_FM<0x1c, 0x03>;
|
|
|
316
|
|
|
317 // Extract a signed bit field /+32
|
|
|
318 def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
|
|
|
319 def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
|
|
|
320
|
|
|
321 // Clear and insert a bit field /+32
|
|
|
322 def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
|
|
|
323 def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
|
|
|
324
|
|
|
325 // Move to multiplier/product register
|
|
|
326 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
|
|
|
327 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
|
|
|
328 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
|
|
|
329 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
|
|
|
330 def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
|
|
|
331 def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
|
|
|
332
|
|
|
333 // Count Ones in a Word/Doubleword
|
|
|
334 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
|
|
|
335 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
|
|
|
336
|
|
|
337 // Set on equal/not equal
|
|
|
338 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
|
|
|
339 def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
|
|
|
340 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
|
|
|
341 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
|
|
|
342
|
|
|
343 // 192-bit x 64-bit Unsigned Multiply and Add
|
|
|
344 let Defs = [P0, P1, P2] in
|
|
|
345 def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
|
|
|
346 ADD_FM<0x1c, 0x11>;
|
|
|
347
|
|
|
348 // 64-bit Unsigned Multiply and Add Move
|
|
|
349 let Defs = [MPL0, P0, P1, P2] in
|
|
|
350 def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
|
|
|
351 ADD_FM<0x1c, 0x10>;
|
|
|
352
|
|
|
353 // 64-bit Unsigned Multiply and Add
|
|
|
354 let Defs = [MPL1, MPL2, P0, P1, P2] in
|
|
|
355 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
|
|
|
356 ADD_FM<0x1c, 0x0f>;
|
|
|
357
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
358 }
|
|
77
|
359
|
|
|
360 }
|
|
|
361
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
362 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
363 // Arbitrary patterns that map to one or more instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
364 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
365
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
366 // extended loads
|
|
77
|
367 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
|
|
|
368 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
|
|
|
369 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
|
|
|
370 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
371
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
372 // hi/lo relocs
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
373 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
374 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
375 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
376 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
377 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
378 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
379
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
380 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
381 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
382 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
383 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
384 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
385 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
386 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
387
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
388 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
389 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
390 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
391 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
392 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
393 (DADDiu GPR64:$hi, tjumptable:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
394 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
395 (DADDiu GPR64:$hi, tconstpool:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
396 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
397 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
398
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
399 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
400 def : WrapperPat<tconstpool, DADDiu, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
401 def : WrapperPat<texternalsym, DADDiu, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
402 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
403 def : WrapperPat<tjumptable, DADDiu, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
404 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
405
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
406 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
407 ZERO_64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
408
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
409 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
410 (BLEZ64 i64:$lhs, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
411 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
412 (BGEZ64 i64:$lhs, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
413
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
414 // setcc patterns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
415 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
416 defm : SetlePats<GPR64, SLT64, SLTu64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
417 defm : SetgtPats<GPR64, SLT64, SLTu64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
418 defm : SetgePats<GPR64, SLT64, SLTu64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
419 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
420
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
421 // truncate
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
422 def : MipsPat<(i32 (trunc GPR64:$src)),
|
|
77
|
423 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
424
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
425 // 32-to-64-bit extension
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
426 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
427 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
428 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
429
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
430 // Sign extend in register
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
431 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
432 (SLL64_64 GPR64:$src)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
433
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
434 // bswap MipsPattern
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
435 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
436
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
437 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
438 // Instruction aliases
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
439 //===----------------------------------------------------------------------===//
|
|
77
|
440 def : MipsInstAlias<"move $dst, $src",
|
|
|
441 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
|
|
|
442 GPR_64;
|
|
|
443 def : MipsInstAlias<"daddu $rs, $rt, $imm",
|
|
|
444 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
|
|
445 0>;
|
|
|
446 def : MipsInstAlias<"dadd $rs, $rt, $imm",
|
|
|
447 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
|
|
448 0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
449 def : MipsInstAlias<"daddu $rs, $imm",
|
|
|
450 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
|
|
|
451 0>;
|
|
|
452 def : MipsInstAlias<"dadd $rs, $imm",
|
|
|
453 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
|
|
|
454 0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
455 def : MipsInstAlias<"add $rs, $imm",
|
|
|
456 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
|
|
|
457 0>;
|
|
|
458 def : MipsInstAlias<"addu $rs, $imm",
|
|
|
459 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
|
|
|
460 0>;
|
|
|
461 def : MipsInstAlias<"dsll $rd, $rt, $rs",
|
|
|
462 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
|
463 ISA_MIPS3;
|
|
|
464 def : MipsInstAlias<"dsubu $rt, $rs, $imm",
|
|
|
465 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
|
|
|
466 InvertedImOperand64:$imm), 0>;
|
|
|
467 def : MipsInstAlias<"dsubi $rs, $rt, $imm",
|
|
|
468 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
|
|
|
469 InvertedImOperand64:$imm),
|
|
|
470 0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
471 def : MipsInstAlias<"dsubi $rs, $imm",
|
|
|
472 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
|
|
|
473 InvertedImOperand64:$imm),
|
|
|
474 0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
475 def : MipsInstAlias<"dsub $rs, $rt, $imm",
|
|
|
476 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
|
|
|
477 InvertedImOperand64:$imm),
|
|
|
478 0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
479 def : MipsInstAlias<"dsub $rs, $imm",
|
|
|
480 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
|
|
|
481 InvertedImOperand64:$imm),
|
|
|
482 0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
483 def : MipsInstAlias<"dsubu $rs, $imm",
|
|
|
484 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
|
|
|
485 InvertedImOperand64:$imm),
|
|
|
486 0>;
|
|
|
487 def : MipsInstAlias<"dsra $rd, $rt, $rs",
|
|
|
488 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
|
489 ISA_MIPS3;
|
|
|
490 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
|
|
|
491 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
|
492 ISA_MIPS3;
|
|
|
493
|
|
|
494 class LoadImm64< string instr_asm, Operand Od, RegisterOperand RO> :
|
|
|
495 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
|
|
|
496 !strconcat(instr_asm, "\t$rt, $imm64")> ;
|
|
|
497 def LoadImm64Reg : LoadImm64<"dli", imm64, GPR64Opnd>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
498
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
499 /// Move between CPU and coprocessor registers
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
500 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
501 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
|
|
77
|
502 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
|
|
|
503 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
|
|
|
504 def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
505 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
506
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
507 // Two operand (implicit 0 selector) versions:
|
|
77
|
508 def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
|
|
509 def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
|
|
510 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
|
|
511 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
512
|
